公开(公告)号：US08102019B1

公开(公告)日：2012-01-24

申请号：US12488179

申请日：2009-06-19

Applicant: Serhii Tumakha ,  Boon Y. Ang ,  Amit Ghia ,  Jan L. de Jong

Inventor： Serhii Tumakha ,  Boon Y. Ang ,  Amit Ghia ,  Jan L. de Jong

IPC: H01L29/00 ,  H01L27/10 ,  H01L23/525 ,  H01L21/768 ,  H01L21/336 ,  H01L21/82

CPC classification number: H01L23/5256 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Abstract translation: 用于半导体集成电路（IC）的熔丝结构包括阳极，其包括覆盖设置在IC的衬底层内的扩散材料的导电材料，其中扩散材料通过至少一个p-n结与衬底层电隔离。 熔丝结构可以包括包含覆盖扩散材料的导电材料的阴极。 熔丝结构还可以包括熔断器，其包括覆盖扩散材料的导电材料，其中熔丝链的第一端耦合到阳极，熔丝链的第二端在第一端的远端处连接到阴极 。

公开(公告)号：US20110210443A1

公开(公告)日：2011-09-01

申请号：US12713855

申请日：2010-02-26

Applicant: Michael J. Hart ,  Jan L. de Jong ,  Paul Y. Wu

Inventor： Michael J. Hart ,  Jan L. de Jong ,  Paul Y. Wu

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1191 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1355 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/36 ,  H01L2224/05552

Abstract: An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract translation: 描述形成半导体器件的方法的实施例，该半导体器件包括在有源层上形成的具有有源层和互连的衬底。 该方法包括：在互连上方形成具有暴露第一金属层的至少一部分的锥形通孔的电介质层; 在所述锥形通孔和所述第一金属层上形成凸起下金属化（UBM）层以形成UBM桶; 以及在介电层和UBM层的一部分上形成电介质盖层。 UBM桶被配置为支撑焊球，并且可以有利地阻挡具有相关入射角的焊球发射的所有α粒子到达IC的有源半导体区域。 因此，减少或消除了诸如存储器单元中的单个事件的混乱的软错误。

公开(公告)号：US07948791B1

公开(公告)日：2011-05-24

申请号：US12354202

申请日：2009-01-15

Applicant: Jan L. de Jong

Inventor： Jan L. de Jong

IPC: G11C11/00

CPC classification number: H03K19/1776 ,  G11C11/412 ,  G11C11/4125

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; and a second inverter having a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the first node being coupled to control terminals of the third transistor and the fourth transistor and the second node being coupled to control the first transistor and the second transistor; wherein the third transistor is implemented with physical dimensions which make the third transistor stronger than the first transistor, or the second transistor is implemented with physical dimensions which make the second transistor stronger than the fourth transistor.

Abstract translation: 公开了一种具有多个存储器单元的存储器阵列，其中每个存储器单元包括第一反相器，其具有耦合在参考电压和用于接收输入数据的第一节点之间的第一晶体管和耦合在第一节点和地之间的第二晶体管; 以及第二反相器，其具有耦合在所述参考电压和用于存储反相输入数据的第二节点之间的第三晶体管和耦合在所述第二节点和地之间的第四晶体管，所述第一节点耦合到所述第三晶体管和所述第四晶体管的控制端子 并且所述第二节点被耦合以控制所述第一晶体管和所述第二晶体管; 其中第三晶体管被实现为具有使得第三晶体管比第一晶体管更强的物理尺寸，或者第二晶体管以使得第二晶体管比第四晶体管更强的物理尺寸来实现。

公开(公告)号：US06868537B1

公开(公告)日：2005-03-15

申请号：US10082991

申请日：2002-02-25

Applicant: Jonathan J. Ho ,  Xin X. Wu ,  Zicheng Gary Ling ,  Jan L. de Jong

Inventor： Jonathan J. Ho ,  Xin X. Wu ,  Zicheng Gary Ling ,  Jan L. de Jong

IPC: G03F1/14 ,  G06F17/50

CPC classification number: G03F1/36 ,  G03F1/68 ,  G06F17/5068 ,  G06F2217/12

Abstract: For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Abstract translation: 对于具有重复结构的IC设备，生成用于制作掩模层的数据库的方法从描述层中的至少一个重复元素的分层数据库开始，围绕重复元素的骨架以及关于在哪里定位的指令 重复骨骼内的元素。 该数据库被修改以产生具有光学邻近校正（OPC）的数据库，用于衍射通过掩模并在IC层上曝光光致抗蚀剂的光的衍射。 使用关于如何将经修改的数据库分割以形成在OPC之后仍然相同的重复元素的指令，包含非重复元素的掩码框架以及用于放置 骨骼中的重复元素。 因此，所得到的掩码数据库小于包含所有重复元素副本的掩码数据库。

公开(公告)号：US06727710B1

公开(公告)日：2004-04-27

申请号：US10109744

申请日：2002-03-28

Applicant: Jan L. de Jong ,  Zicheng G. Ling

Inventor： Jan L. de Jong ,  Zicheng G. Ling

IPC: G01R3126

CPC classification number: G01R31/27

Abstract: A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

Abstract translation: 测试电路包括在IC晶片中，用于测试高电流应力下IC的可靠性。 测试电路包括两个感测晶体管，一个选择晶体管和一个电阻。 电阻器的两端通过两个感测晶体管耦合到两个感测端子。 电阻器的一端还耦合到第一应力输入端子; 电阻器的另一端通过选择晶体管耦合到第二应力输入端子。 当选择测试电路时，感测和选择晶体管导通。 在两个应力输入端子之间形成电流路径，并且可以使用两个感测端子在电阻器两端测量电压差。 行和列选择电路使得能够快速测试这种测试电路阵列中的许多电阻器尺寸和配置。

公开(公告)号：US08149612B1

公开(公告)日：2012-04-03

申请号：US13085420

申请日：2011-04-12

Applicant: Jan L. de Jong

Inventor： Jan L. de Jong

IPC: G11C11/00

CPC classification number: H03K19/1776 ,  G11C11/412 ,  G11C11/4125

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a first inverter comprising a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter comprising a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the second node being coupled to a control terminal of the second transistor. The memory array further comprises a third inverter and a fourth inverter.

Abstract translation: 公开了一种具有多个存储器单元的存储器阵列，其中每个存储器单元包括第一反相器，其具有耦合在参考电压和用于接收输入数据的第一节点之间的第一晶体管和耦合在第一节点和地之间的第二晶体管; 第一反相器，包括耦合在参考电压和用于接收输入数据的第一节点之间的第一晶体管和耦合在第一节点和地之间的第二晶体管; 第二反相器，包括耦合在参考电压和用于存储反相输入数据的第二节点之间的第三晶体管和耦合在第二节点和地之间的第四晶体管，第二节点耦合到第二晶体管的控制端。 存储器阵列还包括第三反相器和第四反相器。

公开(公告)号：US07515452B1

公开(公告)日：2009-04-07

申请号：US11649447

申请日：2007-01-03

Applicant: Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

Inventor： Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

IPC: G11C11/00

CPC classification number: G11C8/04 ,  H03K19/00392 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

Abstract translation: 存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。 多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。 第二存储单元具有第三单元部分和第四单元部分。 第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。 在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。

公开(公告)号：US07453311B1

公开(公告)日：2008-11-18

申请号：US11016657

申请日：2004-12-17

Applicant: Michael L. Hart ,  Patrick Quinn ,  Jan L. de Jong

Inventor： Michael L. Hart ,  Patrick Quinn ,  Jan L. de Jong

IPC: G05F1/10

CPC classification number: G05F3/242

Abstract: A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well regions of the device to compensate for process variations. For some embodiments, if measurement of the performance parameter indicates that the device does not fall within a specified range of operating parameters, the control circuit biases selected well regions to sufficiently alter the operating characteristics of transistors formed therein so that the device falls within the specified range of operating parameters.

Abstract translation: 一种方法和装置补偿半导体器件的制造中的工艺变化。 半导体器件包括测量器件的性能参数的控制电路，并且响应于此选择性地偏置器件的一个或多个阱区域以补偿工艺变化。 对于一些实施例，如果性能参数的测量指示器件不在规定的工作参数范围内，则控制电路偏置所选择的阱区，以充分改变在其中形成的晶体管的工作特性，使得器件落入指定的 操作参数范围。

公开(公告)号：US07312625B1

公开(公告)日：2007-12-25

申请号：US11449197

申请日：2006-06-08

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

IPC: G01R31/00

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2858

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract translation: 描述了用于制造用于超大规模集成（“VLSI”）处理的晶体管的测试电路及其使用方法。 晶体管形成阵列。 第一解码器耦合到晶体管的栅极并被配置为选择性地将电压传递到栅极。 第二解码器耦合到晶体管的漏极区域并且被配置为选择性地将电压传递到晶体管的漏极区域。 第三解码器耦合到晶体管的源极区域并且被配置为选择性地将电压传递到晶体管的源极区域。 第四解码器耦合到晶体管的体区，并且被配置为选择性地将电压传递到晶体管的体区。

公开(公告)号：US07429867B1

公开(公告)日：2008-09-30

申请号：US11032375

申请日：2005-01-10

Applicant: Jan L. de Jong

Inventor： Jan L. de Jong

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G11C29/48 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: Various embodiments of the present invention describe circuits for and methods of detecting a defect in a component formed in a substrate of an integrated circuit. According to one embodiment, a circuit comprises a plurality of components formed in a substrate and coupled in series by a plurality of signal paths extending from a first end to a second end. An input signal coupled to the first end of the first signal path is detected a signal detector coupled to a second end of the first signal path to determine whether there is a defect in a component formed in the substrate. Switching networks at the inputs and the outputs of the plurality signal paths enable determining a particular signal path that had a defect. Alternate embodiments describe circuits for determining the location of a defective component in a signal path. Various methods of detecting defective components are also described.

Abstract translation: 本发明的各种实施例描述了形成在集成电路的衬底中的部件中的缺陷的检测方法和方法。 根据一个实施例，电路包括形成在衬底中的多个部件，并且由从第一端延伸到第二端的多个信号路径串联耦合。 检测耦合到第一信号路径的第一端的输入信号，耦合到第一信号路径的第二端的信号检测器，以确定在衬底中形成的部件中是否存在缺陷。 在多个信号路径的输入和输出处的交换网络使得能够确定具有缺陷的特定信号路径。 替代实施例描述用于确定信号路径中的有缺陷的分量的位置的电路​​。 还描述了检测有缺陷的部件的各种方法。