公开(公告)号：US07638822B1

公开(公告)日：2009-12-29

申请号：US11649448

申请日：2007-01-03

Applicant: Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

Inventor： Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

IPC: H01L27/10 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L27/105 ,  H01L27/11807 ,  H03K19/00338 ,  Y10S257/903

Abstract: A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

Abstract translation: 具有多个晶体管的存储单元具有至少5：1的纵横比，所述多个晶体管被连接以使得存储器单元的节点的数据值恢复到初始值之后的初始值。 高尺寸比在小型设计技术下提供用于SEU容差的存储器单元的节点之间的适当间隔。

公开(公告)号：US07515452B1

公开(公告)日：2009-04-07

申请号：US11649447

申请日：2007-01-03

Applicant: Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

Inventor： Jan L. de Jong ,  Susan Xuan Nguyen ,  Raymond C. Pang

IPC: G11C11/00

CPC classification number: G11C8/04 ,  H03K19/00392 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

Abstract translation: 存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。 多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。 第二存储单元具有第三单元部分和第四单元部分。 第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。 在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。