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    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
    1.
    发明授权
    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits 有权
    用于确定高应力电流对集成电路中导电层和触点的影响的结构和方法

    公开(公告)号：US06842019B1

    公开(公告)日：2005-01-11

    申请号：US10787332

    申请日：2004-02-26

    Applicant: Jan L. de Jong ,  Zicheng G. Ling

    Inventor： Jan L. de Jong ,  Zicheng G. Ling

    IPC: G01R31/27 ,  G01R31/26 ,  G01R27/08

    CPC classification number: G01R31/27

    Abstract: A method of testing reliability in an integrated circuit including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor. Other embodiments include measuring additional resistance values before applying and after removing the high stress current. One embodiment includes applying a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit.

    Abstract translation: 一种在包括测试电路阵列的集成电路中测试可靠性的方法，每个测试电路包括电阻器。 该方法包括从阵列中选择第一测试电路，测量所选择的测试电路中的电阻器的预应力电阻值，在电阻器两端施加高应力电流，去除高应力电流以及测量后应力电阻 电阻值。 其他实施例包括在施加之前和在去除高应力电流之后测量附加电阻值。 一个实施例包括向一个应力输入端施加正电压，然后在施加高应力电流之前和之后测试用于正电压的短检测端。 这些步骤测试了高应力电流是否在测试电路中产生了短路。

    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
    2.
    发明授权
    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits 有权
    用于确定高应力电流对集成电路中导电层和触点的影响的结构和方法

    公开(公告)号：US06867580B1

    公开(公告)日：2005-03-15

    申请号：US10787715

    申请日：2004-02-26

    Applicant: Jan L. de Jong ,  Zicheng G. Ling

    Inventor： Jan L. de Jong ,  Zicheng G. Ling

    IPC: G01R31/27 ,  G01R31/26

    CPC classification number: G01R31/27

    Abstract: A test circuit is included in an IC wafer for testing the reliability of ICS under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

    Abstract translation: IC芯片中包含一个测试电路，用于在高电流应力下测试ICS的可靠性。 测试电路包括两个感测晶体管，一个选择晶体管和一个电阻。 电阻器的两端通过两个感测晶体管耦合到两个感测端子。 电阻器的一端还耦合到第一应力输入端子; 电阻器的另一端通过选择晶体管耦合到第二应力输入端子。 当选择测试电路时，感测和选择晶体管导通。 在两个应力输入端子之间形成电流路径，并且可以使用两个感测端子在电阻器两端测量电压差。 行和列选择电路使得能够快速测试这种测试电路阵列中的许多电阻器尺寸和配置。

    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
    3.
    发明授权
    Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits 有权
    用于确定高应力电流对集成电路中导电层和触点的影响的结构和方法

    公开(公告)号：US06727710B1

    公开(公告)日：2004-04-27

    申请号：US10109744

    申请日：2002-03-28

    Applicant: Jan L. de Jong ,  Zicheng G. Ling

    Inventor： Jan L. de Jong ,  Zicheng G. Ling

    IPC: G01R3126

    CPC classification number: G01R31/27

    Abstract: A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

    Abstract translation: 测试电路包括在IC晶片中，用于测试高电流应力下IC的可靠性。 测试电路包括两个感测晶体管，一个选择晶体管和一个电阻。 电阻器的两端通过两个感测晶体管耦合到两个感测端子。 电阻器的一端还耦合到第一应力输入端子; 电阻器的另一端通过选择晶体管耦合到第二应力输入端子。 当选择测试电路时，感测和选择晶体管导通。 在两个应力输入端子之间形成电流路径，并且可以使用两个感测端子在电阻器两端测量电压差。 行和列选择电路使得能够快速测试这种测试电路阵列中的许多电阻器尺寸和配置。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    4.
    发明授权
    Characterizing circuit performance by separating device and interconnect impact on signal delay 失效
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US07724016B2

    公开(公告)日：2010-05-25

    申请号：US12355988

    申请日：2009-01-19

    Applicant: Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    Inventor： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC: G01R31/02

    CPC classification number: G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    Abstract translation: 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    5.
    发明授权
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US07489152B2

    公开(公告)日：2009-02-10

    申请号：US11498371

    申请日：2006-08-03

    Applicant: Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    Inventor： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC: G01R31/28

    CPC classification number: G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    Abstract translation: 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY
    7.
    发明申请
    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY 失效
    通过分离设备来表征电路性能和对信号延迟的互连影响

    公开(公告)号：US20090121737A1

    公开(公告)日：2009-05-14

    申请号：US12355988

    申请日：2009-01-19

    Applicant: Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    Inventor： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC: G01R31/26 ,  G01R31/02 ,  H01L23/58

    CPC classification number: G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    Abstract translation: 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Method for measuring gate length and drain/source gate overlap
    8.
    发明授权
    Method for measuring gate length and drain/source gate overlap 失效
    测量栅极长度和漏极/源极栅极重叠的方法

    公开(公告)号：US6166558A

    公开(公告)日：2000-12-26

    申请号：US237540

    申请日：1999-01-26

    Applicant: Chun Jiang ,  Wei Long ,  Zicheng G. Ling ,  Yowjuang W. Liu

    Inventor： Chun Jiang ,  Wei Long ,  Zicheng G. Ling ,  Yowjuang W. Liu

    IPC: H01L21/66 ,  H01L29/78

    CPC classification number: H01L22/12

    Abstract: The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX. The invention further calculates source/drain gate overlap L.sub.OV, by setting L.sub.OV =C.sub.OV /C.sub.OX.

    Abstract translation: 本发明提供了一种通过测量栅极电容来计算栅极长度和源极/漏极栅极重叠的方法和装置。 本发明使用先前已知的边缘电容Cfr和单位电容COX。 本发明在栅极被累积偏置时测量栅极电容Cg，并使用公式COV =（Cg-2Cfr）/ 2或COV =（Cgg-Cgb-2Cfr）/ 2求解重叠电容COV。 然后，当栅极/源极/漏极电压被设置为反向偏压并且在源极/漏极和衬底之间施加零电压，并且使用公式Cch = Cg-1求解沟道电容Cch时，本发明测量栅极电容Cg。 2Cfr-2COV。 本发明计算Cch = Cg-2Cfr-2COV的沟道电容Cch，然后计算栅极长度Lg =（2COV + Cch）/ COX和有效栅极长度Leff = Cch / COX的栅极长度。 本发明通过设定LOV = COV / COX，进一步计算源极/漏极栅极重叠LOV。

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