公开(公告)号：US07581124B1

公开(公告)日：2009-08-25

申请号：US11326542

申请日：2006-01-04

Applicant: Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC: G06F1/22

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0401 ,  H03K19/17784

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract translation: PLD包括多个逻辑块，测试电路和测试引脚组。 逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。 在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。

公开(公告)号：US08099691B1

公开(公告)日：2012-01-17

申请号：US12491174

申请日：2009-06-24

Applicant: Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC: G06F17/50

CPC classification number: H03K19/17784

Abstract: A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

Abstract translation: 公开了一种操作集成电路（“IC”）的方法。 该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。 该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

公开(公告)号：US07549139B1

公开(公告)日：2009-06-16

申请号：US10783216

申请日：2004-02-20

Applicant: Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

IPC: G06F17/50 ,  H03K19/00

CPC classification number: H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

Abstract: A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

Abstract translation: 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

公开(公告)号：US07098689B1

公开(公告)日：2006-08-29

申请号：US10666669

申请日：2003-09-19

Applicant: Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC: H03K19/094 ,  H03K19/177 ,  G05F1/10 ,  G11C5/14

CPC classification number: H03K19/17784

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

公开(公告)号：US07562332B1

公开(公告)日：2009-07-14

申请号：US11502939

申请日：2006-08-11

Applicant: Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC: G06F17/50

CPC classification number: H03K19/17784

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract translation: 一种操作可编程逻辑器件的方法，包括以下步骤：使可编程逻辑器件的资源在由可编程逻辑器件实现的电路设计中使用，以及禁用未被使用的可编程逻辑器件的未使用或不活动资源 电路设计。 禁用的步骤可以包括从一个或多个电源端子去耦合未使用或不活动的资源。 或者，禁用步骤可以包括调节施加到未使用或不活动资源的电源电压。 可以响应于由可编程逻辑器件存储的配置数据位和/或响应于用户控制的信号来执行禁用步骤。 可以在可编程逻辑器件的设计时间和/或运行时间期间启动禁用步骤。

公开(公告)号：US07504854B1

公开(公告)日：2009-03-17

申请号：US10783589

申请日：2004-02-20

Applicant: Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

Inventor： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC: H03K19/173 ,  G11C5/14

CPC classification number: H03K19/1778 ,  G11C5/14 ,  H03K19/17784

Abstract: A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

Abstract translation: 一种操作可编程逻辑器件的方法，包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的一个或多个有效块，以及使用降低的电源电压（例如，½VDD）来操作一个或多个不活动的 可编程逻辑器件的块。 可以通过高电压n沟道晶体管向可编程逻辑器件的块提供完整的VDD电源电压和降低的电源电压。 大于VDD的升压电压被施加到n沟道晶体管的栅极，以向有源块提供完整的VDD电源电压。 小于VDD的待机电压被施加到n沟道晶体管的栅极，以向非活动块提供降低的电源电压。 可以在可编程逻辑器件的运行时间和/或设计时间期间确定非活动块。

公开(公告)号：US08155907B1

公开(公告)日：2012-04-10

申请号：US12480488

申请日：2009-06-08

Applicant: Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

Inventor： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

IPC: G06F11/00 ,  G06F19/00 ,  G06F17/40

CPC classification number: G06F17/5045 ,  G06F11/26 ,  G06F2217/86

Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Abstract translation: 公开了在集成电路装置中实现设计功能的方法。 示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。 还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

公开(公告)号：US08130027B1

公开(公告)日：2012-03-06

申请号：US12357703

申请日：2009-01-22

Applicant: Tim Tuan

Inventor： Tim Tuan

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G11C5/147 ,  H03K19/17784 ,  H03K19/17792

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract translation: 提供用于动态检测和补偿集成电路（IC）内的性能变化的装置和方法，用于在任何测试或操作阶段检测IC内的性能变化。 与内部振荡装置结合使用任意的参考信号以建立可用于表征IC的速度参考。 也可以在IC内的多个地理位置内配置动态检测和补偿，从而可以检测和补偿性能变化。 表示IC性能的测试数据可以连续地或以可编程的间隔动态产生，从而可以在IC的生命周期的任何时刻基本上检测和补偿实际上任何源引起的性能变化。

公开(公告)号：US07992020B1

公开(公告)日：2011-08-02

申请号：US12043096

申请日：2008-03-05

Applicant: Tim Tuan ,  Kerry M. Pierce ,  Albert Franceschino

Inventor： Tim Tuan ,  Kerry M. Pierce ,  Albert Franceschino

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

Abstract: Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.

Abstract translation: 描述了使用封装的多芯片集成电路（IC）进行电源管理。 第一集成电路管芯能够具有第一操作模式。 第二集成电路管芯耦合到第一集成电路管芯。 当第一集成电路管芯处于第一操作模式并且第二集成电路管芯处于第二操作模式时，第一集成电路管芯具有低于第二集成电路管芯的功率消耗率。 第一集成电路管芯被配置为用于第二集成电路管芯的电源管理，用于将第二集成电路管芯从第二操作模式放置在待机模式中，并且用于将第二集成电路管芯退回到从待机模式的第二操作模式。

公开(公告)号：US07212462B1

公开(公告)日：2007-05-01

申请号：US10701835

申请日：2003-11-04

Applicant: Tim Tuan

Inventor： Tim Tuan

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGS can under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.

Abstract translation: 提供了降低集成电路晶体管漏电功率的技术。 抑制亚阈值泄漏技术可以应用于驱动晶体管的栅极的存储单元，驱动晶体管源极的存储单元以及驱动晶体管栅极的电平移位器。 在这些技术中，适当的栅极 - 源极电压（V SUB）可以被施加到处于截止状态的晶体管。 重要的是，该晶体管可以驱动晶体管，这显着降低了该晶体管的次阈值泄漏。 这些技术不能使晶体管处于导通状态，从而确保集成电路的高速性能得以保持。