公开(公告)号：US10061339B1

公开(公告)日：2018-08-28

申请号：US15802965

申请日：2017-11-03

申请人： NXP USA, Inc.

发明人： Andre Luis Vilas Boas ,  Richard Titov Lara Saez ,  Ivan Carlos Ribeiro Do Nascimento ,  Marcelo de Paula Campos ,  Pedro Barbosa Zanetta

IPC分类号： G05F3/26 ,  G11C5/14 ,  G05F3/20 ,  H03F3/45 ,  H02M1/08

CPC分类号： G05F3/26 ,  G05F3/205 ,  G11C5/145 ,  G11C5/146 ,  H02M1/083 ,  H02M3/07 ,  H03F3/45475 ,  H03F2200/78

摘要： A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.

公开(公告)号：US10320387B1

公开(公告)日：2019-06-11

申请号：US16146435

申请日：2018-09-28

申请人： NXP USA, INC.

发明人： Ivan Carlos Ribeiro Do Nascimento ,  Armando Gomes Da Silva, Jr.

IPC分类号： H03K19/23 ,  H03K19/08 ,  H03K19/173 ,  H03K19/088

摘要： An integrated circuit includes a digital logic circuit having a first transistor and a second transistor, a replica circuit having a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, and a storage circuit configured to store a static state indicator. The circuit also includes a comparison circuit configured to compare threshold voltages of the first and second transistor of the replica circuit, and having an output coupled to provide the static state indicator to the storage circuit, and a selection circuit configured to provide the state indicator to an input of the digital logic circuit and an input of the replica circuit during a lower power mode and to provide a run mode signal instead of the state indicator to the input of the digital logic signal and the input of the replica circuit during a high power mode.

公开(公告)号：US09984763B1

公开(公告)日：2018-05-29

申请号：US15365041

申请日：2016-11-30

申请人： NXP USA, INC.

发明人： Andre Luis Vilas Boas ,  Richard Titov Lara Saez ,  Ivan Carlos Ribeiro Do Nascimento ,  Javier Mauricio Olarte Gonzalez

IPC分类号： G11C27/02 ,  H03K17/06 ,  H03K5/159

CPC分类号： G11C27/024 ,  H03K5/159

摘要： A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

公开(公告)号：US10396790B1

公开(公告)日：2019-08-27

申请号：US16152611

申请日：2018-10-05

申请人： NXP USA, INC.

发明人： Luis Francisco P. Junqueira De Andrade ,  Ivan Carlos Ribeiro Do Nascimento ,  Armando Gomes Da Silva, Jr. ,  Marcos Da Costa Barros

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K21/38

摘要： An integrated circuit includes a digital logic circuit, a multiplexer (MUX) having a first and a second data input, a control input, and an output coupled to an input of the digital logic circuit. The second data input is coupled to receive a high frequency clock signal. The integrated circuit includes a very low frequency (VLF) clock is configured to provide a VLF clock signal when enabled, and a counter coupled to receive the VLF clock signal and configured to toggle an output of the counter upon counting a predetermined number of cycles of the VLF clock signal. The output of the counter is coupled to the first data input of the MUX. The MUX is configured to provide the first data input as the output of the MUX during a low power mode, and otherwise to provide the second data input as the output of the MUX.

公开(公告)号：US20180151242A1

公开(公告)日：2018-05-31

申请号：US15365041

申请日：2016-11-30

申请人： NXP USA, INC.

发明人： Andre Luis Vilas Boas ,  Richard Titov Lara Saez ,  Ivan Carlos Ribeiro Do Nascimento ,  Javier Mauricio Olarte Gonzalez

IPC分类号： G11C27/02 ,  H03K17/06 ,  H03K5/159

CPC分类号： G11C27/024 ,  H03K5/159

摘要： A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.