-
公开(公告)号：US20240348143A1
公开(公告)日：2024-10-17
申请号：US18299174
申请日：2023-04-12
Applicant: Cisco Technology, Inc.
Inventor： Bibhu Prasad Das , Abhishek Bhat , Kadaba Lakshmikumar , Romesh Kumar Nandwana
CPC classification number: H02M1/0045 , H02M3/073
Abstract: A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.
-
公开(公告)号：US20240339917A1
公开(公告)日：2024-10-10
申请号：US18746752
申请日：2024-06-18
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla , Marcella Carissimi
CPC classification number: H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
-
公开(公告)号：US12018422B2
公开(公告)日：2024-06-25
申请号：US18228978
申请日：2023-08-01
Applicant: WHIRLPOOL CORPORATION
Inventor： Daniel Quinn
IPC: F04D15/00 , D06F34/08 , H02K7/14 , H02M1/10 , H02M1/32 , H02M3/07 , H02P27/04 , D06F34/10 , D06F37/30
CPC classification number: D06F34/08 , H02M1/10 , H02M1/32 , H02M3/073 , H02P27/04 , D06F34/10 , D06F37/304 , H02P2201/09
Abstract: A circuit that increases input voltage to higher output voltage connected to a drive. The circuit can include a power input that receives the input voltage from a power source and at least one capacitor bank connected with the power input. A current-limiting surge suppressor is positioned between the power input and the at least one capacitor bank. The current-limiting surge suppressor includes a first current-limiting path and a second bypass path. A drain, when operable, dissipates the charge of the at least one capacitor bank. The drive is operable in response to the higher voltage output from the at least one capacitor bank.
-
公开(公告)号：US20240204551A1
公开(公告)日：2024-06-20
申请号：US18068338
申请日：2022-12-19
Applicant: Apple Inc.
Inventor： Vijay G Phadke
CPC classification number: H02J7/00714 , H02M3/073 , H02J2207/20
Abstract: A buck-fed current multiplier battery charging circuit can include a buck converter having an input configured to receive an input voltage and an output configured to deliver a regulated current, a current multiplier having an input configured to receive the regulated current from the buck converter and an output configured to deliver a multiple of the regulated current to a battery, wherein the current multiplier comprises one or more flying capacitor stages each including a resonant tank circuit; and controller circuitry coupled to the buck converter that operates switches of the buck converter to produce the regulated current and coupled to the current multiplier that operates switches of the current multiplier to deliver the multiple of the regulated current to the battery.
-
公开(公告)号：US20240120835A1
公开(公告)日：2024-04-11
申请号：US18544466
申请日：2023-12-19
Applicant: pSemi Corporation
Inventor： David GIULIANO , Gregory SZCZESZYNSKI , Raymond BARRETT, JR.
Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
-
Patent Agency Ranking
公开(公告)号：US11875860B2
公开(公告)日：2024-01-16
申请号：US17870714
申请日：2022-07-21
Applicant: Lodestar Licensing Group LLC
Inventor： Alberto Troia , Antonino Mondello
IPC: G11C16/30 , G01R31/3177 , G11C16/14 , G11C16/26 , H02M3/07
Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.
-
公开(公告)号：US11855532B2
公开(公告)日：2023-12-26
申请号：US17901479
申请日：2022-09-01
Applicant: pSemi Corporation
Inventor： Walid Fouad Mohamed Aboueldahab , Aichen Low
IPC: H02M3/07
Abstract: Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a softstart period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.
-
公开(公告)号：US11784561B2
公开(公告)日：2023-10-10
申请号：US17936406
申请日：2022-09-29
Applicant: pSemi Corporation
Inventor： Aichen Low , Gregory Szczeszynski , David Guiliano
IPC: H02M3/07
Abstract: An apparatus for power conversion includes a switching network that controls interconnections between pump capacitors in a capacitor network that has a terminal coupled to a current source, and a charge-management subsystem. In operation, the switching network causes the capacitor network to execute charge-pump operating cycles during each of which the capacitor network adopts different configurations in response to different configurations of the switching network. At the start of a first charge-pump operating cycle, each pump capacitor assumes a corresponding initial state. The charge-management subsystem restores each pump capacitor to the initial state by the start of a second charge-pump operating cycle that follows the first charge-pump operating cycle.
-
公开(公告)号：US11757357B2
公开(公告)日：2023-09-12
申请号：US17714969
申请日：2022-04-06
Applicant: Intel Corporation
Inventor： Takao Oshita , Fabrice Paillet , Rinkle Jain , Jad Rizk , Danny Bronstein , Ahmad Arnaot
IPC: H02M3/07 , G06F1/3234 , H03K5/24 , H02M1/00
CPC classification number: H02M3/073 , G06F1/3234 , H02M1/00 , H02M3/07 , H02M3/072 , H03K5/249 , H02M1/0012 , H02M1/0045 , H02M3/077
Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
-
公开(公告)号：US20230283179A1
公开(公告)日：2023-09-07
申请号：US18073384
申请日：2022-12-01
Applicant: pSemi Corporation
Inventor： Aichen Low , Walid Fouad Mohamed Aboueldahab , Gregory Szczeszynski
CPC classification number: H02M3/073 , G05F3/262 , G05F1/565 , H02M1/0025
Abstract: Circuit embodiments for a switched-capacitor power converter, and/or methods of operation of such a converter, that robustly deal with various startup scenarios, are efficient and low cost, and have quick startup times to steady-state converter operation. Embodiments prevent full charge pump capacitor discharge during shutdown of a converter and/or rebalance charge pump capacitors during a startup period before switching operation by discharging and/or precharging the charge pump capacitors. Embodiments may include a dedicated rebalancer circuit that includes a voltage sensing circuit coupled to an output voltage of a converter, and a balance circuit configured to charge or discharge each charge pump capacitor towards a target steady-state multiple of the output voltage of the converter as a function of an output signal from the voltage sensing circuit indicative of the output voltage. Embodiments prevent or limit current in-rush to a converter during a startup state.
-
-
-
-
-
-
-
-
-
Search Results
1913
records
(took 0.021 seconds)
