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    HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR
    2.
    发明公开
    HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR 审中-公开

    公开(公告)号：US20230195981A1

    公开(公告)日：2023-06-22

    申请号：US17554821

    申请日：2021-12-17

    Applicant: International Business Machines Corporation

    Inventor： Shakti Kapoor ,  Nelson Wu ,  Manoj Dusanapudi

    IPC: G06F30/33 ,  G06F12/0891

    CPC classification number: G06F30/33 ,  G06F12/0891 ,  G06F9/3806

    Abstract: A system, mechanism, tool, programming product, processor, and/or method for generating a hazard in a processor includes: identifying one or more cache lines to invalidate in a second level memory of a processing core in the processor; invalidating, in response to identifying one or more cache lines to invalidate in the second level cache, the one or more identified cache lines in the second level memory; and invalidating, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory. In an aspect the hazard generating mechanism is triggered, preferably on demand, and includes in an approach searching for cache lines in the second level memory that are also in the first level memory.

    Validation of store coherence relative to page translation invalidation
    5.
    发明授权
    Validation of store coherence relative to page translation invalidation 有权

    公开(公告)号：US11620235B1

    公开(公告)日：2023-04-04

    申请号：US17493212

    申请日：2021-10-04

    Applicant: International Business Machines Corporation

    Inventor： Shakti Kapoor ,  Nelson Wu ,  Manoj Dusanapudi

    IPC: G06F12/1027 ,  G06F12/0891 ,  G06F12/0882 ,  G06F7/58 ,  G06F13/16 ,  G06F9/30

    Abstract: Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.

    System and method for testing processor errors
    6.
    发明授权
    System and method for testing processor errors 有权

    公开(公告)号：US10748637B2

    公开(公告)日：2020-08-18

    申请号：US16046163

    申请日：2018-07-26

    Applicant: International Business Machines Corporation

    Inventor： Nelson Wu ,  Manoj Dusanapudi ,  Shakti Kapoor ,  Nandhini Rajaiah

    IPC: G11C29/38 ,  G06F9/30

    Abstract: A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations.

    LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOUNDARIES
    7.
    发明申请
    LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOUNDARIES 审中-公开

    公开(公告)号：US20190287639A1

    公开(公告)日：2019-09-19

    申请号：US16433142

    申请日：2019-06-06

    Applicant: International Business Machines Corporation

    Inventor： Manoj Dusanapudi ,  Shakti Kapoor ,  Nelson Wu

    IPC: G11C29/38 ,  G11C29/36

    Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.

    METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION TABLES
    8.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION TABLES 审中-公开

    公开(公告)号：US20190188146A1

    公开(公告)日：2019-06-20

    申请号：US15843595

    申请日：2017-12-15

    Applicant: International Business Machines Corporation

    Inventor： Manoj Dusanapudi ,  Shakti Kapoor ,  Nelson Wu

    IPC: G06F12/1009 ,  G06F12/1027

    Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.

    Cache coherence validation using delayed fulfillment of L2 requests
    10.
    发明授权
    Cache coherence validation using delayed fulfillment of L2 requests 有权

    公开(公告)号：US12118355B2

    公开(公告)日：2024-10-15

    申请号：US17506122

    申请日：2021-10-20

    Applicant: International Business Machines Corporation

    Inventor： Shakti Kapoor ,  Manoj Dusanapudi ,  Nelson Wu

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0811

    CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0811

    Abstract: Methods and systems for validating cache coherence in a data processing system are described. A processing element may detect a load instruction requesting the processing element to transfer data from a global memory location to a local memory location. The processing element may apply, in response to detecting the load instruction requesting the processing element to transfer data from the global memory location to the local memory location, a delay to the transfer of the data from the global memory location to the local memory location. The processing element may execute the load instruction and transferring the data from the global memory location to the local memory location with the applied delay. The processing element may validate, in response to executing the load instruction and transferring the data with the applied delay, a cache coherence of the data processing system.

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