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    Configurable Interface Circuit
    4.
    发明申请
    Configurable Interface Circuit 有权

    公开(公告)号：US20230064369A1

    公开(公告)日：2023-03-02

    申请号：US17463292

    申请日：2021-08-31

    Applicant: Apple Inc.

    Inventor： Rohit K. Gupta ,  Rohit Natarajan ,  Jurgen M. Schulz ,  Harshavardhan Kaushikkar ,  Connie W. Cheung

    IPC: G06F12/0871 ,  G06F12/02 ,  G06F13/16 ,  H03K19/0175

    Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

    PARALLEL COHERENCE AND MEMORY CACHE PROCESSING PIPELINES
    5.
    发明申请
    PARALLEL COHERENCE AND MEMORY CACHE PROCESSING PIPELINES 审中-公开

    公开(公告)号：US20200081838A1

    公开(公告)日：2020-03-12

    申请号：US16129527

    申请日：2018-09-12

    Applicant: Apple Inc.

    Inventor： Muditha Kanchana ,  Srinivasa Rangan Sridharan ,  Harshavardhan Kaushikkar ,  Sridhar Kotha ,  Brian P. Lilly

    IPC: G06F12/0815 ,  G06F12/0884 ,  G06F12/0855

    Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

    Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
    6.
    发明授权
    Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers 有权
    一致性处理与预杀机制，以避免重复的事务标识符

    公开(公告)号：US09465740B2

    公开(公告)日：2016-10-11

    申请号：US13860885

    申请日：2013-04-11

    Applicant: Apple Inc.

    Inventor： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

    Abstract: An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

    Abstract translation: 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于所接收的读取事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。

    Mechanism for sharing private caches in a SoC
    7.
    发明授权
    Mechanism for sharing private caches in a SoC 有权
    在SoC中共享私有缓存的机制

    公开(公告)号：US09280471B2

    公开(公告)日：2016-03-08

    申请号：US14081549

    申请日：2013-11-15

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

    Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

    FLOW-ID DEPENDENCY CHECKING LOGIC
    8.
    发明申请
    FLOW-ID DEPENDENCY CHECKING LOGIC 有权
    FLOW-ID依赖性检查逻辑

    公开(公告)号：US20140195740A1

    公开(公告)日：2014-07-10

    申请号：US13736245

    申请日：2013-01-08

    Applicant: APPLE INC.

    Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar

    IPC: G06F12/08

    CPC classification number: G06F12/0815 ,  G06F9/46 ,  G06F9/466 ,  G06F12/0811 ,  G06F13/18

    Abstract: Systems and methods for maintaining an order of transactions in the coherence point. The coherence point stores attributes associated with received transactions in an input request queue (IRQ). When a new transaction is received with a device ordered attribute, the IRQ is searched for other entries with the same flow ID as the new transaction. If one or more matches are found, the new transaction entry points to the entry for the most recently received transaction with the same flow ID. The new transaction is prevented from exiting the coherence point until the transaction it points to has been sent to its destination.

    Abstract translation: 在一致性点保持交易顺序的系统和方法。 相干点存储与输入请求队列（IRQ）中的接收事务相关联的属性。 当接收到具有设备排序属性的新事务时，IRQ将搜索与新事务具有相同流ID的其他条目。 如果找到一个或多个匹配，则新的事务条目指向具有相同流ID的最近收到的事务的条目。 新交易被阻止退出连贯点，直到其指向的交易已发送到其目的地。

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