公开(公告)号：US20150067269A1

公开(公告)日：2015-03-05

申请号：US14534842

申请日：2014-11-06

申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD

发明人： Endong WANG ,  Leijun HU ,  Jicheng CHEN ,  Dong ZHANG ,  Weifeng GONG ,  Feng ZHANG

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/082 ,  G06F12/0826 ,  G06F15/17368 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/2542 ,  G06F2212/622

摘要： A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in anode controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node ca roller can support the multiple physical cache coherency domains in a node.

摘要翻译： 一种用于构建具有多个高速缓存一致性域的节点的多处理器系统的方法。 在该系统中，内置阳极控制器的目录需要包括处理器域属性信息，并且可以通过配置连接到处理器的节点控制器的端口的高速缓存一致性域属性来获取信息。 在本文的公开内容中，节点ca滚筒可以支持节点中的多个物理高速缓存一致性域。

公开(公告)号：US07937591B1

公开(公告)日：2011-05-03

申请号：US10280496

申请日：2002-10-25

申请人： Paul L. Master ,  John Watson

发明人： Paul L. Master ,  John Watson

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06F15/17368 ,  H04N21/426 ,  H04N21/435 ,  H04N21/8106 ,  H04N21/8193

摘要： A method and system for adapting a device is disclosed. The method and system comprises providing a data stream to the device to be changed based upon a parameter. In a second aspect an adaptable device is disclosed. The adaptable device comprises an adaptable computerized environment (ACE) for receiving a data stream that allows the device to be changed based upon a parameter. The adaptable device includes a mechanism within the ACE for authorizing the data stream. A system and method in accordance with the present invention provides a hardware device that can be changed based upon a particular parameter such as time and location. In so doing, a provider of the hardware device can provide a more adaptable component which provides more value to the provider. Indeed, it is possible to give away the hardware upfront or even give an incentive to a receiver of the hardware and thereby use the device in a variety of ways.

摘要翻译： 公开了一种用于适配设备的方法和系统。 该方法和系统包括基于参数向要改变的设备提供数据流。 在第二方面，公开了一种适应性装置。 可适应装置包括适应性计算机化环境（ACE），用于接收允许基于参数改变设备的数据流。 适应性设备包括用于授权数据流的ACE内的机制。 根据本发明的系统和方法提供了可以基于诸如时间和位置的特定参数来改变的硬件设备。 在这样做时，硬件设备的提供者可以提供更适应性强的组件，为提供商提供更多的价值。 实际上，可以预先放弃硬件，甚至可以激励硬件的接收器，从而以各种方式使用该设备。

公开(公告)号：US20050138324A1

公开(公告)日：2005-06-23

申请号：US10905100

申请日：2004-12-15

申请人： Pascal Tannhof ,  Jan Slyfield

发明人： Pascal Tannhof ,  Jan Slyfield

IPC分类号： G06F15/00 ,  G06F15/173

CPC分类号： G06F15/17368

摘要： A processing unit having a dual channel bus architecture associated with a specific instruction set, configured to receive an input message and transmit an output message that is identical or derived therefrom. A message consists of one opcode, with or without associated data, used to control each processing unit depending on logic conditions stored in dedicated registers in each unit. Processing units are serially connected but can work simultaneously for a total pipelined operation. This dual architecture is organized around two channels labeled Channel 1 and Channel 2. Channel 1 mainly transmits an input message to all units while Channel 2 mainly transmits the results after processing in a unit as an output message. Depending on the logic conditions, an input message not processed in a processing unit may be transmitted to the next one without any change.

摘要翻译： 一种具有与特定指令集相关联的双通道总线架构的处理单元，其被配置为接收输入消息并发送相同或从其导出的输出消息。 消息由一个操作码组成，具有或不具有关联数据，用于根据存储在每个单元中的专用寄存器中的逻辑条件来控制每个处理单元。 处理单元串联连接，但可以同时工作进行总体流水线操作。 该双重架构围绕标记为通道1和通道2的两个通道组合。通道1主要向所有单元发送输入消息，而通道2主要在以单元处理之后将结果作为输出消息发送。 根据逻辑条件，在处理单元中未处理的输入消息可以被发送到下一个，而没有任何改变。

公开(公告)号：US6126331A

公开(公告)日：2000-10-03

申请号：US869902

申请日：1997-06-05

申请人： Hideaki Komatsu ,  Takeshi Ogasawara

发明人： Hideaki Komatsu ,  Takeshi Ogasawara

IPC分类号： G06F13/00 ,  G06F15/173 ,  G06F9/45

CPC分类号： G06F15/17368

摘要： To generate an optimum communication schedule when data is transmitted or received between processors which constitute a parallel computer or a distributed multiprocessor system.Processors which each perform inter-processor communication are sorted into a plurality of groups. A communication graph is generated whose nodes correspond to the groups and edges correspond to the communications. Communication graphs are generated for distances between nodes from one through N-1. Each communication graph corresponds to a communication step of the inter-processor communication. Communication is grasped as a whole by the communication graph and the edge of the communication graph means the inter-processor communication which is performed in a certain communication step. In this way, the communication can be optimized.

摘要翻译： 当在构成并行计算机或分布式多处理器系统的处理器之间发送或接收数据时，生成最佳通信调度。 每个执行处理器间通信的处理器被分类成多个组。 生成其节点对应于组和边缘对应于通信的通信图。 生成从1到N-1的节点之间的距离的通信图。 每个通信图对应于处理器间通信的通信步骤。 通过通信图来整体地进行通信，通信图的边缘是指在某个通信步骤中执行的处理器间通信。 以这种方式，可以优化通信。

公开(公告)号：US6088758A

公开(公告)日：2000-07-11

申请号：US461167

申请日：1995-06-05

申请人： Mark A. Kaufman ,  Fernando Oliveira

发明人： Mark A. Kaufman ,  Fernando Oliveira

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/12 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17368 ,  G06F12/0824 ,  G06F12/128 ,  G06F2212/272

摘要： A digital data processing system and method with shared, distributed memory transfers data between corresponding data sets within memory. The digital data processing system includes a plurality of processing cells interconnected by a hierarchical network, at least some of the processing cells including a processor and a memory. Each memory provides storage space which is arranged in sets, with each set being capable of holding a plurality of data pages. At least one of the processing cells, as a first processing cell, includes a page distributor for determining when at least a first set in the associated memory has reached a predetermined storage commitment condition (for example, a filled condition). Under such a condition, the page distributor invokes a page-transfer element that selects a candidate processing cell from among the other processing cells and transfers one or more pages from the first set to a corresponding set in the candidate processing cell.

摘要翻译： 具有共享分布式存储器的数字数据处理系统和方法在存储器内的相应数据集之间传送数据。 数字数据处理系统包括通过分级网络互连的多个处理单元，至少一些处理单元包括处理器和存储器。 每个存储器提供以集合排列的存储空间，每个存储空间能够保存多个数据页。 作为第一处理单元的处理单元中的至少一个包括页面分配器，用于确定关联存储器中的至少第一组何时已经达到预定的存储承诺条件（例如，填充状态）。 在这种情况下，页面分配器调用从其他处理单元中选择候选处理单元的页面传送单元，并将一个或多个页面从第一组传送到候选处理单元中的相应组。

公开(公告)号：US5822608A

公开(公告)日：1998-10-13

申请号：US301278

申请日：1994-09-06

申请人： James Warren Dieffenderfer ,  Peter Michael Kogge ,  Paul Amba Wilkinson ,  Nicholas Jerome Schoonover

发明人： James Warren Dieffenderfer ,  Peter Michael Kogge ,  Paul Amba Wilkinson ,  Nicholas Jerome Schoonover

IPC分类号： G06F15/16 ,  F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F13/14 ,  G06F15/173 ,  G06F15/80 ,  G06F15/76

CPC分类号： G06F15/8015 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/803 ,  G06F7/483 ,  F02B2075/027

摘要： Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip implementation in an air cooled environment. The array provided is an N dimensional array of byte wide processing units each coupled with an adequate segment of byte wide memory and control logic. A partitionable section of the array containing several processing units are contained on a silicon chip arranged with "Picket"s, an element of the processing array preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A Picket Processor system (or Subsystem) comprises an array of pickets, a communication network, an I/O system, and a SIMD controller consisting of a microprocessor, a canned routine processor, and a microcontroller that runs the array. The Picket Architecture for SIMD includes set associative processing, parallel numerically intensive processing, with physical array processing similar to image processing, a military picket line analogy fits quite well. Pickets, having a bit parallel processing element, with local memory coupled to the processing element for the parallel processing of information in an associative way where each picket is adapted to perform one element of the associative process. We have provided a way for horizontal association with each picket. The memory of the picket units is arranged in an array. The array of pickets thus arranged comprises a set associative memory. The set associative parallel processing system on a single chip permits a smaller set of `data` out of a larger set to be brought out of memory where an associative operation can be performed on it. This associative operation, typically an exact compare, is performed on the whole set of data in parallel, utilizing the Picket's memory and execution unit.

摘要翻译： 多处理器并行计算系统和字节串行SIMD处理器并行架构用于并行阵列处理，具有适应于空气冷却环境中芯片实现的简化架构。 所提供的阵列是一个字节宽的处理单元的N维阵列，每个都与足够的字节宽的存储器和控制逻辑段相连。 包含几个处理单元的阵列的可分割部分包含在以“Picket”排列的硅芯片上，处理阵列的元件优选地由具有本地存储器的组合处理元件组成，用于在时钟周期中处理位并行字节的位 。 拾音处理器系统（或子系统）包括一组阵列，通信网络，I / O系统和由微处理器，固定例程处理器和运行阵列的微控制器组成的SIMD控制器。 SIMD的Picket架构包括集合关联处理，并行数字密集处理，物理阵列处理类似于图像处理，军事线路类比相当合适。 具有位并行处理元件的拾取器具有耦合到处理元件的本地存储器，用于以关联方式并行处理信息，其中每个纠察器适于执行关联处理的一个元件。 我们为每个纠察队提供横向联系的方法。 纠察单位的存储器被排列成阵列。 这样布置的桩的阵列包括一组联合存储器。 单个芯片上的集合关联并行处理系统允许较大集合中的较小的“数据”集合被从存储器中提取出来，其中可以执行关联操作。 利用Picket的存储器和执行单元，并行地对整个数据集合执行这种关联操作，通常是精确的比较。

公开(公告)号：US5594868A

公开(公告)日：1997-01-14

申请号：US407853

申请日：1995-03-21

申请人： Junji Nakagoshi ,  Tatsuo Higuchi ,  Shinichi Kato ,  Toshimitsu Ando ,  Masaaki Iwasaki

发明人： Junji Nakagoshi ,  Tatsuo Higuchi ,  Shinichi Kato ,  Toshimitsu Ando ,  Masaaki Iwasaki

IPC分类号： G06F12/14 ,  G06F15/173 ,  G06F13/14 ,  G06F15/16 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.

摘要翻译： 并行处理器系统包括：接收缓冲器指针控制器，用于产生其中写入接收到的分组的接收缓冲器区域的地址，并且用于检查接收缓冲区域中是否没有空间区域; 能够由指令处理器设置和复位的丢弃命令位; 接收到的分组丢弃判断单元，用于从丢弃命令比特和从接收缓冲器指针控制器提供的信息判断所接收的分组是否被写入，暂停或丢弃; 以及接收控制器，用于根据接收到的分组丢弃判断单元的判断，控制将接收到的分组写入接收缓冲区。 利用这种布置，即使接收缓冲区中没有用于存储接收到的分组的空间区域，或者即使接收到的分组由于接收处理单元的故障而不能接收，也可以在接收处理器中丢弃所接收的分组 单元。

公开(公告)号：US5594866A

公开(公告)日：1997-01-14

申请号：US618037

申请日：1996-03-18

申请人： Steven F. Nugent

发明人： Steven F. Nugent

IPC分类号： G06F15/173 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L45/26 ,  G06F15/17368 ,  G06F15/17381 ,  H04L45/06 ,  H04L45/40

摘要： A parallel processing computer system having an improved architecture for communication of information between nodes. The computer system of the present invention comprises at least three nodes; each of the three nodes for processing information. Each of the nodes comprises a routing means for routing information between nodes. The routing means allow reservation of a route through the network of nodes. Messages may then be transmitted from an origin node to a destination node over the reserved route. Use of a route reservation system reduces requirements for buffering of information at intermediate nodes on a route, improves message passing latency and increases node-to-node bandwidth. The present invention teaches communication of messages between nodes in a synchronous manner using a common strobe signal. The strobe signal is modified by regenerating alternate edges of the signal in order to eliminate pulse shrinkage of the strobe signal.

摘要翻译： 具有用于在节点之间进行信息通信的改进的架构的并行处理计算机系统。 本发明的计算机系统包括至少三个节点; 每个三个节点用于处理信息。 每个节点包括用于在节点之间路由信息的路由装置。 路由装置允许预留通过节点网络的路由。 然后，消息可以通过保留路由从原始节点发送到目的地节点。 使用路由预留系统减少了对路由中的中间节点的信息缓冲的需求，改善了消息传递延迟并增加了节点到节点的带宽。 本发明使用公共选通信号以同步方式教导节点之间的消息的通信。 通过再生信号的交替边缘来修改选通信号，以消除选通信号的脉冲收缩。

公开(公告)号：US5497465A

公开(公告)日：1996-03-05

申请号：US368242

申请日：1995-01-03

申请人： Danny Chin ,  Donald J. Sauer ,  Dietrich Meyerhofer ,  Kazuo Katsuki

发明人： Danny Chin ,  Donald J. Sauer ,  Dietrich Meyerhofer ,  Kazuo Katsuki

IPC分类号： G02B6/00 ,  G06E1/00 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17368 ,  G06F15/8007

摘要： MIMD and pipeline processing is executed by entering data and control signals into processing chips in the form of optical signals, and entering multi-bit information (data and control signals) in parallel and at high speed on the basis of non-coherence of light beams. The efficiency of MIMD processing function has been improved by expanding data transfer buses between processors and output buses in place of data and control signal input buses that have become unnecessary. A processing chip for receiving optical signals consists of a large number of cells dedicated for vector computations, and/or a large number of cells dedicated for vector computations and/or cells dedicated for arithmetic and logical computations. A processing chip for wide applications ranging from vector computations to logical computations by employing a construction combining both processors.

摘要翻译： 通过将数据和控制信号以光信号的形式输入到处理芯片中，并且基于光束的非相干性并行地并且高速地进入多位信息（数据和控制信号）来执行MIMD和流水线处理 。 通过扩展处理器和输出总线之间的数据传输总线来代替不必要的数据和控制信号输入总线，改进了MIMD处理功能的效率。 用于接收光信号的处理芯片由专用于矢量计算的大量单元和/或专用于矢量计算的大量单元和/或专用于算术和逻辑计算的单元组成。 一种用于广泛应用的处理芯片，从矢量计算到逻辑计算，通过采用结合两个处理器的结构。

公开(公告)号：US5450603A

公开(公告)日：1995-09-12

申请号：US993218

申请日：1992-12-18

申请人： Daniel Davies

发明人： Daniel Davies

IPC分类号： G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17368 ,  G06F15/8015

摘要： A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units. A bidirectional register can be connected between each processing unit and the bus, so that a processing unit can be selected to provide data to the bus by selecting its bidirectional register. Similarly, each processing unit can include a memory that can be selected with a write enable signal so that a set of processing units can be selected to receive and store in memory data from the bus.

摘要翻译： SIMD并行处理器包括互连其处理单元的两种类型的电路：一种将处理单元互连成阵列，使得每个处理单元可以将数据传送到阵列中的相邻处理单元并且可以从相邻处理单元接收数据; 处理单元可以例如以一维阵列相互连接。 另一种互连电路包括总线电路，以允许在向处理单元传送数据和从处理单元传送数据时更大的自由度。 连接到总线是一个寄存器，从而可以通过首先将数据从一个处理单元传输到寄存器，然后将数据从寄存器传输到另一个处理单元，从而在处理单元之间传输数据。 或者存储在寄存器中的数据可以发送到子集或所有处理单元。 类似地，控制电路本身可以在总线上提供数据以传送到一个，一个子集或全部处理单元。 可以在每个处理单元和总线之间连接双向寄存器，从而可以通过选择其双向寄存器来选择处理单元来向总线提供数据。 类似地，每个处理单元可以包括可以用写入使能信号选择的存储器，从而可以选择一组处理单元以从总线接收和存储存储器数据。