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公开(公告)号：US20190294541A1
公开(公告)日：2019-09-26
申请号：US16436635
申请日：2019-06-10
Applicant: Apple Inc.
Inventor： Ali Sazegari , Charles E. Tucker , Jeffry E. Gonion , Gerard R. Williams, III , Chris Cheng-Chieh Lee
IPC: G06F12/08 , H03M7/30 , G06F12/0886
Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
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2.发明申请
公开(公告)号：US20160092398A1
公开(公告)日：2016-03-31
申请号：US14704421
申请日：2015-05-05
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion , Charles E. Tucker , Alexander C. Klaiber
CPC classification number: G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/3013 , G06F9/3838
Abstract: In an embodiment, a processor may implement a vector instruction set including a conditional termination instruction (CTerm). The CTerm instruction may take two source operands and compare them according to a specified condition, updating flags as a result of the instruction. The flags may be used to affect predicate vector generation to control vectorized loop execution. In an embodiment, the vector instruction set may also include a conditional termination predicate instruction (CTPred). The CTPred instruction may take a pair of predicate vectors and a set of flags as operands, and may generate: a predicate vector to control parallel processing of vector elements, and a set of flags to control further loop processing. Either instruction may be used to efficiently manage vector loops in various embodiments, or the instructions may be used together.
Abstract translation: 在一个实施例中，处理器可以实现包括条件终止指令（CTerm）的向量指令集。 CTerm指令可以采用两个源操作数，并根据指定的条件进行比较，作为指令的结果更新标志。 标志可用于影响谓词向量生成以控制向量化循环执行。 在一个实施例中，向量指令集还可以包括条件终止谓词指令（CTPred）。 CTPred指令可以采用一对谓词向量和一组标志作为操作数，并且可以生成：用于控制向量元素的并行处理的谓词向量，以及用于控制进一步的循环处理的一组标志。 在各种实施例中可以使用任一指令来有效地管理向量循环，或者可以一起使用指令。
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公开(公告)号：US20240311319A1
公开(公告)日：2024-09-19
申请号：US18674203
申请日：2024-05-24
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US10331558B2
公开(公告)日：2019-06-25
申请号：US15663115
申请日：2017-07-28
Applicant: Apple Inc.
Inventor： Ali Sazegari , Charles E. Tucker , Jeffry E. Gonion , Gerard R. Williams, III , Chris Cheng-Chieh Lee
Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
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公开(公告)号：US20160092217A1
公开(公告)日：2016-03-31
申请号：US14704396
申请日：2015-05-05
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion , Charles E. Tucker , Alexander C. Klaiber
IPC: G06F9/30
CPC classification number: G06F9/30021 , G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/30094 , G06F9/3013 , G06F9/325
Abstract: In an embodiment, a processor may implement a vector instruction set including one or more compare break instructions. The compare break instruction may take a pair of operands which may be compared to determine loop termination conditions, and may output a predicate vector indicating which vector elements correspond to loop iterations that are executed and which vector elements correspond to loop iterations that are not executed. The predicate vector may serve as a predicate to vector instructions forming the body of the loop, correctly executing the specified number of iterations. The compare break instruction may be coded to check for a variety of conditions (e.g. equal, not equal, greater than, less than, etc.). In an embodiment, the compare break instruction may take a predicate operand as well, which may be combined with the predicate vector produced by the comparison operations to produce the output vector.
Abstract translation: 在一个实施例中，处理器可以实现包括一个或多个比较中断指令的向量指令集。 比较中断指令可以采用一对可以与确定循环终止条件进行比较的操作数，并且可以输出指示哪些向量元素对应于执行的循环迭代的谓词向量，哪些向量元素对应于不执行的循环迭代。 谓词向量可以作为形成循环体的向量指令的谓词，正确执行指定数量的迭代。 比较中断指令可以被编码以检查各种条件（例如相等，不等于，大于，小于等）。 在一个实施例中，比较中断指令也可以采用谓词操作数，其可以与由比较操作产生的谓词向量组合以产生输出向量。
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公开(公告)号：US12007920B2
公开(公告)日：2024-06-11
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11803471B2
公开(公告)日：2023-10-31
申请号：US17821312
申请日：2022-08-22
Applicant: Apple Inc.
Inventor： Per H. Hammarlund , Lior Zimet , Sergio Kolor , Sagi Lahav , James Vash , Gaurav Garg , Tal Kuzi , Jeffry E. Gonion , Charles E. Tucker , Lital Levy-Rubin , Dany Davidov , Steven Fishwick , Nir Leshem , Mark Pilip , Gerard R. Williams, III , Harshavardhan Kaushikkar , Srinivasa Rangan Sridharan
IPC: G06F12/08 , G06F12/0831 , G06F12/128 , G06F12/0811 , G06F12/0815 , G06F12/109 , G06F13/28 , G06F13/16 , G06F13/40 , G06F15/173 , G06F15/78
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0815 , G06F12/109 , G06F12/128 , G06F13/161 , G06F13/1668 , G06F13/28 , G06F13/4068 , G06F15/17368 , G06F15/7807 , G06F2212/305 , G06F2212/657
Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.
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公开(公告)号：US20230251985A1
公开(公告)日：2023-08-10
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11630789B2
公开(公告)日：2023-04-18
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20190034333A1
公开(公告)日：2019-01-31
申请号：US15663115
申请日：2017-07-28
Applicant: Apple Inc.
Inventor： Ali Sazegari , Charles E. Tucker , Jeffry E. Gonion , Gerard R. Williams, III , Chris Cheng-Chieh Lee
CPC classification number: G06F12/08 , G06F12/00 , G06F12/0886 , G06F13/00 , G06F2212/1016 , G06F2212/401 , H03M7/30 , H03M7/3088
Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
