公开(公告)号：US12085611B2

公开(公告)日：2024-09-10

申请号：US17285614

申请日：2018-10-16

申请人： Minima Processor Oy

发明人： Lauri Koskinen ,  Navneet Gupta ,  Jesse Simonsson

IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/3173

CPC分类号： G01R31/3177 ,  G01R31/31712 ,  G01R31/31725 ,  G01R31/3173

摘要： The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value. The method comprises making said one or more adaptive processing paths form test output values on the basis of the respective test input values input to them, and forming a set of test output signals by collecting said test output values given by said one or more adaptive processing paths. The method comprises examining said set of test output signals, and forming a test result on the basis of said examining, and using said test result to select and set an operating parameter value for said operating parameter.

公开(公告)号：US11894848B2

公开(公告)日：2024-02-06

申请号：US17311186

申请日：2018-12-05

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta ,  Lauri Koskinen

IPC分类号： H03K3/037 ,  G01R31/317 ,  G01R31/3177

CPC分类号： H03K3/037 ,  G01R31/3177 ,  G01R31/31725

摘要： A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

公开(公告)号：US12113530B2

公开(公告)日：2024-10-08

申请号：US17311197

申请日：2018-12-05

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta

IPC分类号： H03K19/17736 ,  H03K5/15 ,  H03K17/28

CPC分类号： H03K19/1774 ,  H03K5/15093 ,  H03K17/28

摘要： A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit (301) for a time during which the change generated through said controllable data event injection point (503) propagates to said first register circuit.

公开(公告)号：US11558039B2

公开(公告)日：2023-01-17

申请号：US16768443

申请日：2017-12-01

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta

IPC分类号： H03K3/037 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/21

摘要： A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

公开(公告)号：US11953970B2

公开(公告)日：2024-04-09

申请号：US17425001

申请日：2019-01-23

申请人： Minima Processor Oy

发明人： Matthew Turnquist ,  Navneet Gupta ,  Lauri Koskinen ,  Tuomas Hollman

IPC分类号： G06F1/00 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/30 ,  H03K19/00

CPC分类号： G06F1/3296 ,  G06F1/3206 ,  G06F11/3072 ,  H03K19/0008

摘要： A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

公开(公告)号：US11929746B2

公开(公告)日：2024-03-12

申请号：US16768486

申请日：2017-12-01

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta

IPC分类号： H03K3/037

CPC分类号： H03K3/0372 ,  H03K3/0375

摘要： Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

公开(公告)号：US11699012B2

公开(公告)日：2023-07-11

申请号：US17297623

申请日：2018-11-27

申请人： MINIMA PROCESSOR OY

发明人： Navneet Gupta

IPC分类号： G06F30/3312 ,  G06F30/394 ,  H03K5/13 ,  H03K5/19 ,  G06F119/12 ,  H03K19/20

CPC分类号： G06F30/3312 ,  G06F30/394 ,  H03K5/13 ,  H03K5/19 ,  G06F2119/12 ,  H03K19/20

摘要： Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

公开(公告)号：US20220382581A1

公开(公告)日：2022-12-01

申请号：US17769979

申请日：2019-10-18

申请人： MINIMA PROCESSOR OY

发明人： Lauri Koskinen ,  Navneet Gupta ,  Risto Anttila ,  Samuli Tuoriniemi

IPC分类号： G06F9/48 ,  G06F1/3206 ,  G06F1/3296 ,  G01R31/317 ,  G01R31/30

摘要： The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.