公开(公告)号：US20240345162A1

公开(公告)日：2024-10-17

申请号：US18755800

申请日：2024-06-27

申请人： Qorvo US, Inc.

发明人： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Ryan Lee Bunch

IPC分类号： G01R31/3177 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G11C29/32 ,  G11C29/56

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31724 ,  G01R31/318572 ,  G01R31/3187 ,  G11C29/32 ,  G11C2029/5602

摘要： A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

公开(公告)号：US20240259023A1

公开(公告)日：2024-08-01

申请号：US18635134

申请日：2024-04-15

申请人： Texas Instruments Incorporated

发明人： Timothy Paul Duryea

IPC分类号： H03K19/23 ,  G01R31/317 ,  H03H7/06 ,  H03K3/037

CPC分类号： H03K19/23 ,  G01R31/31712 ,  H03H7/06 ,  H03K3/037

摘要： Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

公开(公告)号：US11913990B2

公开(公告)日：2024-02-27

申请号：US17094129

申请日：2020-11-10

申请人： Advantest Corporation

发明人： Olaf Pöppe ,  Klaus-Dieter Hilliges ,  Alan Krech

IPC分类号： G06F11/07 ,  G06F11/30 ,  G01R31/3183 ,  G01R31/319 ,  G01R31/317 ,  G01R31/3177 ,  G06F13/20 ,  G06F11/273

CPC分类号： G01R31/318307 ,  G01R31/3177 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31724 ,  G01R31/31905 ,  G01R31/31907 ,  G01R31/31908 ,  G01R31/31926 ,  G06F11/2733 ,  G06F13/20

摘要： An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

公开(公告)号：US11768238B2

公开(公告)日：2023-09-26

申请号：US17362319

申请日：2021-06-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

CPC分类号： G01R31/3172 ,  G01R31/3177 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

公开(公告)号：US20230236244A1

公开(公告)日：2023-07-27

申请号：US17582207

申请日：2022-01-24

申请人： Quantum Machines

发明人： Avishai Zvi ,  Ori Weber ,  Nissim Ofek

IPC分类号： G01R31/317 ,  G06N10/20 ,  G06N10/60

CPC分类号： G01R31/31703 ,  G06N10/20 ,  G06N10/60 ,  G01R31/31712

摘要： In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

公开(公告)号：US20180019709A1

公开(公告)日：2018-01-18

申请号：US15633375

申请日：2017-06-26

申请人： NXP B.V.

发明人： Henricus Hubertus van den Berg ,  Michiel Alexander Hallie ,  Joannes Theodorus van der Heiden

IPC分类号： H03F1/02 ,  H03F3/50 ,  H02M1/08

CPC分类号： H03F1/0255 ,  G01R31/3004 ,  G01R31/31712 ,  G01R31/31924 ,  H02M1/082 ,  H03F3/50 ,  H03K19/018521

摘要： An integrated circuit and method are provided. The integrated circuit comprises: a digital core configured to output a first voltage signal: and a first input/output cell: wherein the first input/output cell is configured to convert the first voltage signal to a first current signal and provide the first current signal to circuitry external to the integrated circuit.

公开(公告)号：US20170059656A1

公开(公告)日：2017-03-02

申请号：US15350902

申请日：2016-11-14

申请人： Dell Products L.P.

发明人： Umesh Chandra ,  Timothy Thinh Mai

IPC分类号： G01R31/317 ,  G01R31/3177

CPC分类号： G01R31/31703 ,  G01R31/31708 ,  G01R31/31712 ,  G01R31/31716 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/31907 ,  G06F11/2221

摘要： A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.

摘要翻译： 背板测试系统包括耦合到测试设备机箱并包括第一连接器系统，第二连接器系统和连接第一连接器系统和第二连接器系统的通道的测试背板。 测试设备底盘上的第一测试设备插槽中的第一测试设备接合第一连接器系统，并为第一连接器系统提供环回电路。 第二测试设备在测试设备底盘上的第二测试设备插槽中接合第二连接器系统。 第二测试设备通过测试背板上的通道发送测试信号，使得测试信号被提供给第一测试设备上的环回电路并通过通道接收回来。 第二个测试设备分析接收到的测试信号，以确定测试背板上的通道的测试符合性。

公开(公告)号：US09568546B2

公开(公告)日：2017-02-14

申请号：US13982471

申请日：2012-02-15

申请人： Paul D. Franzon

发明人： Paul D. Franzon

IPC分类号： G01R31/317

CPC分类号： G01R31/31712 ,  G01R31/31725

摘要： An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

摘要翻译： 提供集成电路（IC）芯片。 IC芯片包括通过其发送输出信号的信号输出和接收输入数据信号的信号输入。 IC船上还包括一个通过电路，用于在IC芯片测试期间将信号输出耦合到信号输入端。 此外，延迟电路在IC芯片的测试期间产生第一定时信号和第二定时信号。 第二定时信号根据测试参数从第一定时信号延迟。 第一定时信号通过信号输出触发测试信号的传输，第二定时信号通过信号输入触发所接收的测试信号的采样。

公开(公告)号：US20140143620A1

公开(公告)日：2014-05-22

申请号：US13846132

申请日：2013-03-18

申请人： SK HYNIX INC.

发明人： Byung Deuk JEON

IPC分类号： G01R31/317

CPC分类号： G01R31/31712 ,  G01R31/31905 ,  G01R31/31924 ,  G11C29/1201 ,  G11C29/40 ,  G11C29/48

摘要： A semiconductor apparatus includes a data output unit and a test output unit. The data output unit outputs a plurality of data, through a plurality of data lines, to a plurality of input/output pads. The test output unit receives one of the plurality of data and a plurality of output data, which is output to the plurality of input/output pads, and outputs the received data to a probe pad in a probe test mode.

摘要翻译： 半导体装置包括数据输出单元和测试输出单元。 数据输出单元通过多条数据线将多个数据输出到多个输入/输出焊盘。 测试输出单元接收多个数据中的一个和输出到多个输入/输出焊盘的多个输出数据，并且以探针测试模式将接收到的数据输出到探针焊盘。

公开(公告)号：US20130314102A1

公开(公告)日：2013-11-28

申请号：US13982471

申请日：2012-02-15

申请人： Paul D. Franzon

发明人： Paul D. Franzon

IPC分类号： G01R31/317

CPC分类号： G01R31/31712 ,  G01R31/31725

摘要： An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

摘要翻译： 提供集成电路（IC）芯片。 IC芯片包括通过其发送输出信号的信号输出和接收输入数据信号的信号输入。 IC船上还包括一个通过电路，用于在IC芯片测试期间将信号输出耦合到信号输入端。 此外，延迟电路在IC芯片的测试期间产生第一定时信号和第二定时信号。 第二定时信号根据测试参数从第一定时信号延迟。 第一定时信号通过信号输出触发测试信号的传输，第二定时信号通过信号输入触发所接收的测试信号的采样。