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公开(公告)号:US20230315662A1
公开(公告)日:2023-10-05
申请号:US18044257
申请日:2021-08-27
Applicant: Qorvo US, Inc.
Inventor: Nadim Khlat , Christopher Truong Ngo , Alexander Wayne Hietala
IPC: G06F13/362 , H04L12/40 , G06F13/42
CPC classification number: G06F13/362 , G06F13/4282 , H04L12/40195
Abstract: A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.
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公开(公告)号:US20200341939A1
公开(公告)日:2020-10-29
申请号:US16549116
申请日:2019-08-23
Applicant: Qorvo US, Inc.
IPC: G06F13/42 , H04L12/40 , H04L12/403 , G06F13/362
Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.
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公开(公告)号:US10558607B2
公开(公告)日:2020-02-11
申请号:US15886209
申请日:2018-02-01
Applicant: Qorvo US, Inc.
Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.
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公开(公告)号:US10123286B2
公开(公告)日:2018-11-06
申请号:US15479956
申请日:2017-04-05
Applicant: Qorvo US, Inc.
Inventor: Nadim Khlat , Alexander Wayne Hietala
Abstract: An outphasing power management circuit for radio frequency (RF) beamforming is disclosed. The outphasing power management circuit includes a first outphasing amplifier branch consisting of a plurality of first power amplifiers and a second outphasing amplifier branch consisting of a plurality of second power amplifiers. A controller operates the first outphasing amplifier branch and the second outphasing amplifier branch as a pair of outphasing power amplifiers. The first outphasing amplifier branch generates a plurality of first output signals, and the second outphasing amplifier branch generates a plurality of second output signals. The first output signals and the second output signals are transmitted in an RF beam without being combined. As such, it is possible to support RF beamforming with a reduced number of power amplifiers and/or direct current (DC) to DC converters, thus helping to improve efficiency and reduce cost.
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公开(公告)号:US20180007645A1
公开(公告)日:2018-01-04
申请号:US15479956
申请日:2017-04-05
Applicant: Qorvo US, Inc.
Inventor: Nadim Khlat , Alexander Wayne Hietala
CPC classification number: H04W52/42 , H03F1/0283 , H03F1/0294 , H03F3/195 , H03F3/245 , H03F3/68 , H03F2200/451 , H04B1/0458 , H04B7/0617 , H04B10/50577 , H04B10/50597 , H04B17/11 , H04L27/02
Abstract: An outphasing power management circuit for radio frequency (RF) beamforming is disclosed. The outphasing power management circuit includes a first outphasing amplifier branch consisting of a plurality of first power amplifiers and a second outphasing amplifier branch consisting of a plurality of second power amplifiers. A controller operates the first outphasing amplifier branch and the second outphasing amplifier branch as a pair of outphasing power amplifiers. The first outphasing amplifier branch generates a plurality of first output signals, and the second outphasing amplifier branch generates a plurality of second output signals. The first output signals and the second output signals are transmitted in an RF beam without being combined. As such, it is possible to support RF beamforming with a reduced number of power amplifiers and/or direct current (DC) to DC converters, thus helping to improve efficiency and reduce cost.
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公开(公告)号:US20170111089A1
公开(公告)日:2017-04-20
申请号:US15233359
申请日:2016-08-10
Applicant: Qorvo US, Inc.
Inventor: Nadim Khlat , Alexander Wayne Hietala
CPC classification number: H04B7/0413 , H04B1/00 , H04B7/0452 , H04B7/0617 , Y02D70/00
Abstract: An apparatus for a multiple-input multiple-output (MIMO) architecture is disclosed. The apparatus includes a first splitter-combiner (S-C) having a first transmission line port, a first transmit (TX) port, and a first receive (RX) port. Also included is a first N-plexer having a first power amplifier (PA) input, a first RX output, and a first antenna output for coupling to a first antenna. A first PA is coupled between the first TX port and the PA input, wherein the first RX output is coupled to the first RX port.
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公开(公告)号:US12182052B2
公开(公告)日:2024-12-31
申请号:US18154127
申请日:2023-01-13
Applicant: Qorvo US, Inc.
Inventor: Christopher Truong Ngo , Alexander Wayne Hietala , Nadim Khlat
Abstract: Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed.
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公开(公告)号:US20230198801A1
公开(公告)日:2023-06-22
申请号:US17552497
申请日:2021-12-16
Applicant: Qorvo US, Inc.
Inventor: Christopher Truong Ngo , Nadim Khlat , Alexander Wayne Hietala
CPC classification number: H04L12/40019 , G06F13/4282 , H04L12/40013 , H04L12/40084
Abstract: A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.
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公开(公告)号:US20200151125A1
公开(公告)日:2020-05-14
申请号:US16414007
申请日:2019-05-16
Applicant: Qorvo US, Inc.
Inventor: Christopher Truong Ngo , Alexander Wayne Hietala
Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.
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公开(公告)号:US10579128B2
公开(公告)日:2020-03-03
申请号:US15443236
申请日:2017-02-27
Applicant: Qorvo US, Inc.
IPC: G06F1/3287 , G06F13/364 , H02M3/07 , G06F13/42 , G06F13/40
Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.
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