公开(公告)号：US20230358805A1

公开(公告)日：2023-11-09

申请号：US18163236

申请日：2023-02-01

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Teng SHI ,  Kang ZHAO

IPC分类号： G01R31/317

CPC分类号： G01R31/31704 ,  G01R31/31701 ,  G01R31/31722

摘要： A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.

公开(公告)号：US11808809B2

公开(公告)日：2023-11-07

申请号：US16961229

申请日：2018-11-23

申请人： Robert Bosch GmbH

发明人： Carsten Hermann

IPC分类号： G01R31/3167 ,  G01R31/317

CPC分类号： G01R31/3167 ,  G01R31/3172 ,  G01R31/31701 ,  G01R31/31703

摘要： An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.

公开(公告)号：US11796591B1

公开(公告)日：2023-10-24

申请号：US17712651

申请日：2022-04-04

申请人： Ambarella International LP

发明人： Praveen Jaini ,  Hsin-Wu Hsu ,  Hejia Yan

IPC分类号： G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/31724 ,  G01R31/317 ,  G01R31/31701 ,  G01R31/31721 ,  G01R31/318555

摘要： An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.

公开(公告)号：US11768238B2

公开(公告)日：2023-09-26

申请号：US17362319

申请日：2021-06-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177

CPC分类号： G01R31/3172 ,  G01R31/3177 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

公开(公告)号：US11733295B2

公开(公告)日：2023-08-22

申请号：US17473393

申请日：2021-09-13

申请人： International Business Machines Corporation

发明人： Arun Joseph ,  Wolfgang Roesner ,  Viresh Paruthi ,  Shiladitya Ghosh ,  Spandana Venkata Rachamalla

IPC分类号： G06F30/30 ,  G01R31/317 ,  G01R31/3183

CPC分类号： G01R31/31705 ,  G01R31/31701 ,  G01R31/31704 ,  G01R31/318314

摘要： A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

公开(公告)号：US11686768B2

公开(公告)日：2023-06-27

申请号：US17375013

申请日：2021-07-14

申请人： Test Research, Inc.

发明人： Ching-Chih Lin ,  Hsin-Wei Huang

IPC分类号： G01R31/3177 ,  G01R31/28 ,  G01R27/26 ,  G01R31/317 ,  G01R31/319 ,  G01R31/50

CPC分类号： G01R31/3177 ,  G01R27/2605 ,  G01R31/282 ,  G01R31/2832 ,  G01R31/2834 ,  G01R31/31701 ,  G01R31/31715 ,  G01R31/31723 ,  G01R31/31907 ,  G01R31/31908 ,  G01R31/31926 ,  G01R31/50

摘要： The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

公开(公告)号：US20180328988A1

公开(公告)日：2018-11-15

申请号：US15775734

申请日：2016-03-16

申请人： Hewlett-Packard Development Company, L.P.

发明人： John L McWilliams

IPC分类号： G01R31/317 ,  G11C29/46 ,  G11C29/14

CPC分类号： G01R31/31701 ,  G11C29/02 ,  G11C29/04 ,  G11C29/14 ,  G11C29/46

摘要： In some examples, a method of controlling a transition between a functional mode and a test mode of a logic chip includes enabling a clock input of a disable circuit in response to an indication that the logic chip is in the functional mode. In response to the clock input of the disable circuit being enabled, a transition from the functional mode of the logic chip to the test mode of the logic chip is prevented. The clock input of the disable circuit is disabled in response to an indication that the logic chip is in the test mode. In response to detecting a condition of the logic chip that renders information in a storage element inaccessible, the transition of the logic chip from the functional mode to the test mode is enabled.

公开(公告)号：US10054638B2

公开(公告)日：2018-08-21

申请号：US15348402

申请日：2016-11-10

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Gary L. Swoboda

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F11/22 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317 ,  G06F11/27 ,  G06F11/267 ,  H04L12/26 ,  G06F11/36

CPC分类号： G01R31/3177 ,  G01R31/31701 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318533 ,  G01R31/318538 ,  G01R31/318544 ,  G06F11/22 ,  G06F11/267 ,  G06F11/27 ,  G06F11/36 ,  G06F11/3656 ,  G06F2201/88 ,  H04L43/50

摘要： Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

公开(公告)号：US20170184673A1

公开(公告)日：2017-06-29

申请号：US15133013

申请日：2016-04-19

申请人： SK hynix Inc.

发明人： Haeng Seon CHAE

IPC分类号： G01R31/3177 ,  G01R31/317

CPC分类号： G11C29/46 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/3177 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/56012 ,  G11C2029/1208

摘要： A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

公开(公告)号：US20170115338A1

公开(公告)日：2017-04-27

申请号：US15336687

申请日：2016-10-27

申请人： NVIDIA CORPORATION

发明人： Sailendra Chadalavda ,  Shantanu Sarangi ,  Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Dan Smith ,  Jue Wu ,  Mahmut Yilmaz

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/2607 ,  G01R31/2803 ,  G01R31/2806 ,  G01R31/2834 ,  G01R31/31701 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/00

摘要： In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.