公开(公告)号：US12123908B1

公开(公告)日：2024-10-22

申请号：US18367333

申请日：2023-09-12

申请人： PROTEANTECS LTD.

发明人： Eyal Fayneh ,  Guy Redler ,  Shai Cohen ,  Evelyn Landman

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3177

CPC分类号： G01R31/2896 ,  G01R31/31727 ,  G01R31/3177

摘要： Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.

公开(公告)号：US20240038602A1

公开(公告)日：2024-02-01

申请号：US18376956

申请日：2023-10-05

申请人： PROTEANTECS LTD.

发明人： Eyal FAYNEH ,  Guy REDLER ,  Evelyn LANDMAN

IPC分类号： H01L21/66

CPC分类号： H01L22/26 ,  H01L22/34

摘要： An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

公开(公告)号：US11385282B2

公开(公告)日：2022-07-12

申请号：US16764056

申请日：2018-11-15

申请人： PROTEANTECS LTD.

发明人： Evelyn Landman ,  Shai Cohen ,  Yahel David ,  Eyal Fayneh ,  Inbar Weintrob

IPC分类号： G01R31/28 ,  G01R31/30

摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

公开(公告)号：US12072376B2

公开(公告)日：2024-08-27

申请号：US17712698

申请日：2022-04-04

申请人： proteanTecs Ltd.

发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman ,  Ishai Zeev Cohen ,  Shaked Rahamim ,  Alex Khazin

IPC分类号： G01R31/30 ,  G01R31/3173 ,  H01L23/538 ,  H03K19/003

CPC分类号： G01R31/3016 ,  G01R31/3173 ,  H01L23/5386 ,  H03K19/00323

摘要： An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

公开(公告)号：US20240003968A1

公开(公告)日：2024-01-04

申请号：US18369171

申请日：2023-09-17

申请人： PROTEANTECS LTD.

发明人： Evelyn LANDMAN ,  Yahel DAVID ,  Eyal FAYNEH ,  Shai COHEN ,  Yair TALKER

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/31707 ,  G01R31/2803 ,  G01R31/2894 ,  G01R31/31718 ,  G06N3/08

摘要： A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

公开(公告)号：US11740281B2

公开(公告)日：2023-08-29

申请号：US17703438

申请日：2022-03-24

申请人： PROTEANTECS LTD.

发明人： Eyal Fayneh ,  Edi Shmueli ,  Alexander Burlak ,  Evelyn Landman ,  Inbar Weintrob ,  Yahel David ,  Shai Cohen ,  Guy Redler

IPC分类号： G01R31/28

CPC分类号： G01R31/2853

摘要： An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

公开(公告)号：US20220268644A1

公开(公告)日：2022-08-25

申请号：US17630995

申请日：2020-07-29

申请人： PROTEANTECS LTD.

发明人： Eyal FAYNEH ,  Guy REDLER ,  Evelyn LANDMAN ,  Inbar WEINTROB ,  Yahel DAVID ,  Faten TANASRA

IPC分类号： G01K15/00 ,  G01K7/32

摘要： A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.

公开(公告)号：US11619551B1

公开(公告)日：2023-04-04

申请号：US17750637

申请日：2022-05-23

申请人： PROTEANTECS LTD.

发明人： Eyal Fayneh ,  Guy Redler ,  Shaked Rahamim ,  Evelyn Landman

IPC分类号： G01K7/00 ,  G01K7/01 ,  G01K15/00

摘要： A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.

公开(公告)号：US20230046999A1

公开(公告)日：2023-02-16

申请号：US17862142

申请日：2022-07-11

申请人： PROTEANTECS LTD.

发明人： Evelyn LANDMAN ,  Shai COHEN ,  Yahel DAVID ,  Eyal FAYNEH ,  Inbar WEINTROB

IPC分类号： G01R31/28 ,  G01R31/30

摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

公开(公告)号：US20220343048A1

公开(公告)日：2022-10-27

申请号：US17607974

申请日：2020-05-13

申请人： PROTEANTECS LTD.

发明人： Eyal FAYNEH ,  Guy REDLER ,  Yahel DAVID ,  Inbar WEINTROB ,  Evelyn LANDMAN

IPC分类号： G06F30/367

摘要： Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.