公开(公告)号：US12025658B2

公开(公告)日：2024-07-02

申请号：US17246065

申请日：2021-04-30

申请人： Bitmain Development Inc.

发明人： Christos Vezyrtzis ,  Peter Holm ,  Steve Beccue

IPC分类号： G01R31/3177 ,  G01R31/26 ,  G01R31/30 ,  H03K3/03

CPC分类号： G01R31/3177 ,  G01R31/26 ,  G01R31/3004 ,  G01R31/3016 ,  H03K3/0315

摘要： Embodiments of the invention provide for integrated circuits for testing one or more transistors for process variation effects. According to an embodiment, the integrated circuit can include: a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes two ring oscillators, a first multiplexer, and a first divide-by-two circuit; a multiplexer stage; a divide-by-two circuit stage; a second multiplexer; a second divide-by-two circuit; and frequency measurement circuit. According to another embodiment, the integrated circuit can include: a first shift register including a plurality of devices-under-test; a second shift register including a plurality of static latches; a first multiplexer configured to receive outputs from each of the plurality of DUTs; a second multiplexer configured to receive outputs from each of the plurality of static latches; and a comparator configured to compare an output from the first multiplexer with an output from the second multiplexer.

公开(公告)号：US11841395B2

公开(公告)日：2023-12-12

申请号：US17862142

申请日：2022-07-11

申请人： PROTEANTECS LTD.

发明人： Evelyn Landman ,  Shai Cohen ,  Yahel David ,  Eyal Fayneh ,  Inbar Weintrob

IPC分类号： G01R31/28 ,  G01R31/30

CPC分类号： G01R31/2881 ,  G01R31/3016

摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

公开(公告)号：US11803230B2

公开(公告)日：2023-10-31

申请号：US17813533

申请日：2022-07-19

申请人： Kandou Labs, S.A.

发明人： Armin Tajalli

IPC分类号： G06F1/00 ,  G06F1/3296 ,  G05F1/46 ,  G06F1/324 ,  G01R31/30 ,  H04L25/02

CPC分类号： G06F1/3296 ,  G01R31/3004 ,  G01R31/3016 ,  G05F1/462 ,  G06F1/324 ,  H04L25/0272

摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

公开(公告)号：US20170299651A1

公开(公告)日：2017-10-19

申请号：US15378663

申请日：2016-12-14

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Sylvain Clerc

IPC分类号： G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/3016 ,  G01R31/31725 ,  H03K5/133 ,  H03K19/00369

摘要： A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

公开(公告)号：US09128153B2

公开(公告)日：2015-09-08

申请号：US14474439

申请日：2014-09-02

申请人： Altera Corporation

发明人： Brian Fox

IPC分类号： H03K19/00 ,  G01R31/3177 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/177

CPC分类号： G01R31/3177 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/17764

摘要： A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

摘要翻译： 描述了用于测试集成电路（IC）中的一组电路的方法。 IC包括用于可配置地执行多个操作的多个可配置电路。 该方法将IC配置为以一组满足一组评估标准的测试路径在用户模式下运行。 每个测试路径包括用于可控地存储存储元件接收的信号的可控存储元件。 该方法在用户模式下操作IC。 该方法读取存储在存储元件中的值，以确定该组电路是否在指定的性能限制内运行。

公开(公告)号：US08917108B2

公开(公告)日：2014-12-23

申请号：US13822126

申请日：2011-09-14

申请人： Dominik Weiss

发明人： Dominik Weiss

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G05B23/02

CPC分类号： G01R31/2851 ,  G01R31/3016 ,  G01R31/31721 ,  G01R31/31725 ,  G05B23/0218

摘要： A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay.

摘要翻译： 一种监控集成电路工作参数的装置。 通过比较比较元件的至少两个输入端的输入信号的切换状态，至少在比较元件的一个输出处产生信号，该信号指示至少一个操作参数已经下降或已经超过预定阈值 。 两个输入信号由至少两个操作参数相关的设备产生，并且其切换行为根据至少一个操作参数的当前值而经历时间延迟。 预定义的时间延迟具有这样的值，使得当超过操作参数的预定义阈值时，输入信号中的一个基于时间延迟在时间信号的时间内为比较元件预定的时间改变其切换状态。

公开(公告)号：US08631290B2

公开(公告)日：2014-01-14

申请号：US13327561

申请日：2011-12-15

申请人： Bardia Zandian ,  Murali Annavaram

发明人： Bardia Zandian ,  Murali Annavaram

IPC分类号： G01R31/28

CPC分类号： G01R31/3016

摘要： An automated guardband compensation system automatically compensates for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit automatically and repeatedly requests: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test.

摘要翻译： 自动保护带补偿系统自动补偿时钟数据处理电路的保护带的劣化，同时该电路连接在数据处理系统中。 控制电路自动重复地请求：切换电路，在时钟数据处理电路连接在数据处理系统内的情况下，在数据处理系统内从数据处理路径切换时钟数据处理电路内的关键路径; 一个防护带测试电路，用于测试关键路径的保护带，同时将关键路径切换出数据处理路径; 当测试结果指示保护带中的材料劣化时，用于增加保护带的保护带补偿电路; 以及在测试之后将关键路径切换回数据处理路径的切换电路。

公开(公告)号：US08392859B2

公开(公告)日：2013-03-05

申请号：US12687809

申请日：2010-01-14

申请人： Chun Kit Ng ,  Kenneth S. McElvain

发明人： Chun Kit Ng ,  Kenneth S. McElvain

IPC分类号： G06F17/50

CPC分类号： G01R31/3016 ,  G01R31/31705 ,  G01R31/318364 ,  G06F11/3648 ,  G06F17/5022

摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

摘要翻译： 描述了使用复制逻辑和触发逻辑进行调试的方法和系统。 编译电路的表示。 选择一个或多个信号进行触发，并将触发逻辑插入电路。 电路的一部分被选择用于复制。 电路的所选部分被复制，并且插入延迟逻辑以将输入延迟到电路的复制部分。 电路的表示被重新编译并编程到硬件设备中。 然后可以调用调试器。 选择一个或多个触发信号。 对于每个选定的触发信号，选择一个或多个状态来设置触发条件。 然后可以运行硬件设备。 当触发条件发生时，电路的复制部分将被暂停。 然后可以记录电路的复制部分中的寄存器的状态和导致触发条件的步骤序列。

公开(公告)号：US08261222B2

公开(公告)日：2012-09-04

申请号：US12744525

申请日：2008-11-17

申请人： Yuichi Nakamura

发明人： Yuichi Nakamura

IPC分类号： G06F17/50

CPC分类号： G06F11/24 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318525

摘要： Using fabrication-time variation predicting means that predicts this fact, the variation is predicted beforehand at the design stage prior to fabrication and is stored in variation prediction storage means. Rather than measuring a delay, testing an operation is performed (by a pass/fail determination) by actual-speed logic operation testing means for checking, after fabrication, whether a flip-flop (FF) operates at a specified operation frequency. As a result, the variation is estimated using the non-operation flip-flop (FF) information and the predicted value of the variation from the fabrication-time variation predicting means, and a delay value which corrects for the variation is inserted into a fabricated semiconductor integrated circuit by post-fabrication delay insertion position/value determining means using the variation value that has been estimated.

摘要翻译： 使用预测该事实的制造时间变化预测装置，预先在制造之前的设计阶段预测变化，并将其存储在变化预测存储装置中。 不是测量延迟，而是通过实际速度逻辑运算测试装置（通过通过/失败确定）来测试操作，用于在制造之后检查触发器（FF）是否以指定的操作频率操作。 结果，使用非操作触发器（FF）信息和来自制造时变化预测装置的变化的预测值来估计变化，并且将修正该变化的延迟值插入制造 半导体集成电路通过后制造延迟插入位置/值确定装置使用已经估计的变化值。

公开(公告)号：US08224604B1

公开(公告)日：2012-07-17

申请号：US12539372

申请日：2009-08-11

申请人： Bharadwaj Amrutur ,  Bishnu Prasad Das

发明人： Bharadwaj Amrutur ,  Bishnu Prasad Das

IPC分类号： G01R29/00 ,  G06F11/26

CPC分类号： G01R31/3016

摘要： A system and method to measure a delay of an individual logic gate in an unmodified form on a chip using a digitally reconfigurable ring oscillator (RO) that is on the chip is provided. A system of linear equations is established for different configuration settings of the ring oscillator and solved to determine a delay of an individual gate.

摘要翻译： 提供了一种使用芯片上的数字可重构环路振荡器（RO）来测量芯片上未修改形式的单个逻辑门的延迟的系统和方法。 针对环形振荡器的不同配置设置建立线性方程组，并求解确定单个门的延迟。