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    Integrated circuit margin measurement and failure prediction device
    1.
    发明授权
    Integrated circuit margin measurement and failure prediction device 有权

    公开(公告)号：US11385282B2

    公开(公告)日：2022-07-12

    申请号：US16764056

    申请日：2018-11-15

    申请人： PROTEANTECS LTD.

    发明人： Evelyn Landman ,  Shai Cohen ,  Yahel David ,  Eyal Fayneh ,  Inbar Weintrob

    IPC分类号： G01R31/28 ,  G01R31/30

    摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

    Integrated circuit I/O integrity and degradation monitoring
    3.
    发明授权
    Integrated circuit I/O integrity and degradation monitoring 有权

    公开(公告)号：US10740262B2

    公开(公告)日：2020-08-11

    申请号：US16729680

    申请日：2019-12-30

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Evelyn Landman ,  Shai Cohen ,  Guy Redler ,  Inbar Weintrob

    IPC分类号： G06F3/00 ,  G06F13/16 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    摘要： An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

    Efficient integrated circuit simulation and testing
    4.
    发明授权
    Efficient integrated circuit simulation and testing 有权

    公开(公告)号：US11132485B2

    公开(公告)日：2021-09-28

    申请号：US17254468

    申请日：2019-06-19

    申请人： PROTEANTECS LTD.

    发明人： Evelyn Landman ,  Yair Talker ,  Eyal Fayneh ,  Yahel David ,  Shai Cohen ,  Inbar Weintrob

    IPC分类号： G06F30/30 ,  G06F30/3312 ,  G06F111/08 ,  G06F119/22 ,  G06F119/06

    摘要： A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

    Integrated circuit workload, temperature, and/or sub-threshold leakage sensor
    5.
    发明授权
    Integrated circuit workload, temperature, and/or sub-threshold leakage sensor 有权

    公开(公告)号：US12092684B2

    公开(公告)日：2024-09-17

    申请号：US18215828

    申请日：2023-06-29

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Inbar Weintrob ,  Evelyn Landman ,  Yahel David ,  Shai Cohen ,  Guy Redler

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2853

    摘要： An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

    Integrated circuit margin measurement and failure prediction device
    6.
    发明授权
    Integrated circuit margin measurement and failure prediction device 有权

    公开(公告)号：US11841395B2

    公开(公告)日：2023-12-12

    申请号：US17862142

    申请日：2022-07-11

    申请人： PROTEANTECS LTD.

    发明人： Evelyn Landman ,  Shai Cohen ,  Yahel David ,  Eyal Fayneh ,  Inbar Weintrob

    IPC分类号： G01R31/28 ,  G01R31/30

    CPC分类号： G01R31/2881 ,  G01R31/3016

    摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

    Integrated circuit I/O integrity and degradation monitoring
    9.
    发明授权
    Integrated circuit I/O integrity and degradation monitoring 有权

    公开(公告)号：US11275700B2

    公开(公告)日：2022-03-15

    申请号：US16988993

    申请日：2020-08-10

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Evelyn Landman ,  Shai Cohen ,  Guy Redler ,  Inbar Weintrob

    IPC分类号： G06F13/16 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    摘要： An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.