知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

63 条记录 (耗时 0.022 秒)

    Level converter circuit
    3.
    发明授权
    Level converter circuit 有权

    公开(公告)号：US09780762B2

    公开(公告)日：2017-10-03

    申请号：US15173293

    申请日：2016-06-03

    申请人： SOCIONEXT INC.

    发明人： Tomohiko Koto ,  Kenichi Konishi ,  Osamu Uno

    IPC分类号： H03L5/00 ,  H03K3/356

    CPC分类号： H03K3/356086 ,  H03K3/35613 ,  H03K3/356165 ,  H03K3/356182

    摘要： A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

    BUFFER CIRCUIT AND VOLTAGE GENERATOR USING THE SAME
    4.
    发明申请
    BUFFER CIRCUIT AND VOLTAGE GENERATOR USING THE SAME 审中-公开

    公开(公告)号：US20170141767A1

    公开(公告)日：2017-05-18

    申请号：US15286969

    申请日：2016-10-06

    申请人： ALi Corporation

    发明人： Wei-Chieh FANG ,  Chien-Yuan LU

    IPC分类号： H03K3/356 ,  H02M3/07

    CPC分类号： H03K3/356017 ,  H02M1/08 ,  H02M3/07 ,  H03K3/356086

    摘要： A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.

    Flip-flop, integrated circuit, and flip-flop resetting method
    6.
    发明申请
    Flip-flop, integrated circuit, and flip-flop resetting method 有权
    触发器，集成电路和触发器复位方法

    公开(公告)号：US20070146031A1

    公开(公告)日：2007-06-28

    申请号：US11374183

    申请日：2006-03-14

    申请人： Makoto Mori

    发明人： Makoto Mori

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356008 ,  G06F1/24 ,  H03K3/356086

    摘要： A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a reset operation by detecting a change in a power supply voltage includes a state retaining node that stores a HIGH level voltage or a LOW level voltage, and a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node.

    摘要翻译： 提供了一种触发器，其消除了复位布线以防止LSI中的布线的复杂化或增加用于信号布线的通道数量，使用该布线的集成电路和触发器复位方法。 通过检测电源电压的变化执行复位操作的触发器包括存储高电平电压或低电平电压的状态保持节点和检测超过电源电压变化的复位信号生成电路 预定值以产生用于重置状态保持节点的数据存储状态的复位信号。

    System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator
    7.
    发明授权
    System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator 有权
    用于提供用于与调节单端相位内插器的串行链路的低抖动数据接收器的系统和方法

    公开(公告)号：US07233173B1

    公开(公告)日：2007-06-19

    申请号：US10973743

    申请日：2004-10-26

    申请人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

    发明人： Laurence D. Lewicki ,  Amjad T. Obeidat ,  Nicolas Nodenot

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/222 ,  H03K3/356034 ,  H03K3/356086 ,  H03K5/003 ,  H03K5/082

    摘要： A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

    摘要翻译： 公开了一种用于提供包括低抖动数据接收器的时钟和数据恢复电路的系统和方法。 低抖动数据接收机包括相位内插器，放大器单元和数据采样比较器。 相位内插器和放大器单元为数据采样比较器提供相对免受电源噪声的单端时钟信号。 数据采样比较器由于电源噪声而以最小的抖动对输入数据流进行采样。 数据采样比较器消耗的静态功耗比电流模式逻辑D触发器少，并且还具有与互补金属氧化物半导体（CMOS）逻辑兼容的输出电平。

    Sense amplifier circuit using then film transistors
    8.
    发明授权
    Sense amplifier circuit using then film transistors 失效
    感应放大器电路，然后使用胶片晶体管

    公开(公告)号：US5036231A

    公开(公告)日：1991-07-30

    申请号：US517352

    申请日：1990-05-01

    申请人： Minoru Kanbara

    发明人： Minoru Kanbara

    IPC分类号： H03K19/23 ,  G11C7/06 ,  G11C19/00 ,  H03K3/356

    CPC分类号： G11C7/1087 ,  G11C7/065 ,  H03K3/35606 ,  H03K3/356086

    摘要： A sense amplifier circuit includes an amplifier including first and second inverter circuits which each have a pair of thin film transistors and are connected in a cross-coupled configuration, a precharging thin film transistor connected between the first and second inverter circuits, input transfer gates respectively connected between the first and second inverter circuits and first and second input terminals, and output transfer gate respectively connected between the first and second inverter circuits and first and second input terminals. With the above construction, the precharging thin film transistor is made active to precharge the amplifier and then the transfer gates are operated to permit an input signal to be input to the amplifier, thereby causing the input signal to be discriminated between two values and amplified.

    摘要翻译： 读出放大器电路包括：放大器，包括第一和第二反相器电路，每个反相器电路各自具有一对薄膜晶体管并以交叉耦合的形式连接，分别连接在第一和第二反相器电路之间的预充电薄膜晶体管，输入传输门 连接在第一和第二反相器电路以及分别连接在第一和第二反相器电路与第一和第二输入端子之间的输出传输门。 利用上述结构，预充电薄膜晶体管被激活以对放大器预充电，然后操作传输门以允许将输入信号输入到放大器，从而使输入信号在两个值之间被区分并被放大。