公开(公告)号：US09871503B2

公开(公告)日：2018-01-16

申请号：US15665070

申请日：2017-07-31

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Kazuyuki Nakanishi

IPC分类号： H03K3/356 ,  H03K3/012 ,  H03K3/037

CPC分类号： H03K3/356121 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356026 ,  H03K3/35606

摘要： A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

公开(公告)号：US09300506B2

公开(公告)日：2016-03-29

申请号：US14592054

申请日：2015-01-08

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： Kenji Arai

IPC分类号： H04L27/06 ,  H03L7/00 ,  G06F13/42 ,  G06F1/12 ,  H03K19/096 ,  H04L7/00 ,  H03K3/356 ,  H03K19/00 ,  H04L7/033 ,  H03K19/0185

CPC分类号： H04L27/066 ,  G06F1/12 ,  G06F13/42 ,  H03K3/35606 ,  H03K3/356156 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/096 ,  H03L7/00 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/033

摘要： A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.

公开(公告)号：US09294075B2

公开(公告)日：2016-03-22

申请号：US14199561

申请日：2014-03-06

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Wataru Uesugi

IPC分类号： H03K3/356 ,  H03K3/012

CPC分类号： H03K3/012 ,  H03K3/35606

摘要： To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.

摘要翻译： 提供一种能够执行扫描测试并包括能够减少信号延迟的逻辑电路的半导体器件。 半导体器件包括组合电路，每个保持提供给组合电路的第一数据或从组合电路输出的第二数据的顺序电路，每个保持提供给相应的顺序电路的第一数据的第一存储器电路并且保持来自相应顺序的第二数据输出 电路和第二存储器电路通过将从第一存储器电路中的一个提供的第一数据或第二数据提供给第一存储器电路中的另一个而将第一存储器电路串联电连接。 第二存储电路包括控制向节点提供第一数据或第二数据的第一开关，电连接到该节点的电容器以及控制第一数据或第二数据从该节点输出的第二开关。

公开(公告)号：US20140312950A1

公开(公告)日：2014-10-23

申请号：US14199611

申请日：2014-03-06

申请人： FUJITSU LIMITED

发明人： Satoshi TANABE ,  Kenichi KAWASAKI

IPC分类号： H03K3/356

CPC分类号： H03K3/35606 ,  H03K3/012

摘要： A circuit including: an input stage that includes a first input unit into which input data is input and a pair of first output units and is driven by a first power-supply voltage; a pair of first gate elements that includes first transistors, and is driven by a clock that includes a second power-supply voltage that is lower than the first power-supply voltage; a first latch circuit that includes a pair of second input units, and is driven by the first power-supply voltage; a pair of second gate elements that includes second transistors, and is driven by an inverted clock of the clock; and a second latch circuit that includes a pair of third input units, and a third output unit that outputs one of a pair of pieces of data, and is driven by the first power-supply voltage.

摘要翻译： 一种电路，包括：输入级，包括输入数据输入到其中的第一输入单元和一对第一输出单元，并由第一电源电压驱动; 一对第一栅极元件，包括第一晶体管，并由包括低于第一电源电压的第二电源电压的时钟驱动; 第一锁存电路，包括一对第二输入单元，并由第一电源电压驱动; 一对第二栅极元件，包括第二晶体管，并由时钟的反相时钟驱动; 以及包括一对第三输入单元的第二锁存电路和输出一对数据之一并由第一电源电压驱动的第三输出单元。

公开(公告)号：US08816739B2

公开(公告)日：2014-08-26

申请号：US12765469

申请日：2010-04-22

申请人： Taiki Uemura ,  Yoshiharu Tosaka

发明人： Taiki Uemura ,  Yoshiharu Tosaka

IPC分类号： H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/013 ,  H03K3/35606

摘要： There is provided a semiconductor device having: a latch circuit (103, 104) having a plurality of data holding nodes; a first capacitance element (C) connected to the first data holding node (A) included in the plurality of data holding nodes; and a first switch element (SW2) provided between the first data holding node (A) and the first capacitance element (C).

摘要翻译： 提供了一种具有：具有多个数据保持节点的锁存电路（103,104）的半导体器件; 连接到包括在所述多个数据保持节点中的所述第一数据保持节点（A）的第一电容元件（C） 以及设置在第一数据保持节点（A）和第一电容元件（C）之间的第一开关元件（SW2）。

公开(公告)号：US08587356B2

公开(公告)日：2013-11-19

申请号：US13403597

申请日：2012-02-23

申请人： Shayan Zhang ,  William C. Moyer ,  Ravindraraj Ramaraju

发明人： Shayan Zhang ,  William C. Moyer ,  Ravindraraj Ramaraju

IPC分类号： H03K3/00

CPC分类号： H03K3/35606 ,  H03K3/356008

摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.

摘要翻译： 公开了一种系统，电子电路和方法。 方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据 基于电源门控操作模式。 在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据 在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

公开(公告)号：US08471595B1

公开(公告)日：2013-06-25

申请号：US13353383

申请日：2012-01-19

申请人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin ,  Michael R. Ouellette

发明人： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin ,  Michael R. Ouellette

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K3/35606 ,  G06F7/68 ,  H03K19/1737

摘要： A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.

摘要翻译： 可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 并联栅极和附加栅极的输出端连接到反馈回路。 反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。 因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。

公开(公告)号：US20110148463A1

公开(公告)日：2011-06-23

申请号：US12966513

申请日：2010-12-13

申请人： Kiyoshi Kato ,  Jun Koyama

发明人： Kiyoshi Kato ,  Jun Koyama

IPC分类号： H03K19/173

CPC分类号： H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

摘要翻译： 提供了一种新颖的非易失性锁存电路和使用非易失性锁存电路的半导体器件。 锁存电路具有环形结构，其中第一元件的输出电连接到第二元件的输入，并且第二元件的输出通过第二晶体管电连接到第一元件的输入端。 使用使用氧化物半导体作为沟道形成区域的半导体材料的晶体管作为开关元件，并且提供电容器以电连接到晶体管的源电极或漏电极，由此锁存电路的数据可以 并且可以形成非易失性锁存电路。

公开(公告)号：US20100213998A1

公开(公告)日：2010-08-26

申请号：US12765469

申请日：2010-04-22

申请人： Taiki Uemura ,  Yoshiharu Tosaka

发明人： Taiki Uemura ,  Yoshiharu Tosaka

IPC分类号： H03K3/356

CPC分类号： H03K3/35625 ,  H03K3/013 ,  H03K3/35606

摘要： There is provided a semiconductor device having: a latch circuit (103, 104) having a plurality of data holding nodes; a first capacitance element (C) connected to the first data holding node (A) included in the plurality of data holding nodes; and a first switch element (SW2) provided between the first data holding node (A) and the first capacitance element (C).

摘要翻译： 提供了一种具有：具有多个数据保持节点的锁存电路（103,104）的半导体器件; 连接到包括在所述多个数据保持节点中的所述第一数据保持节点（A）的第一电容元件（C） 以及设置在第一数据保持节点（A）和第一电容元件（C）之间的第一开关元件（SW2）。

公开(公告)号：US5638018A

公开(公告)日：1997-06-10

申请号：US459786

申请日：1995-06-02

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K3/356

CPC分类号： H03K3/35606 ,  H03K3/356156

摘要： A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input. The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period .epsilon., and then the output changing states to match its data input after the period .epsilon. if a signal is received at its clock input having a period greater than .epsilon.. With a pulse applied at the clock input having a width less than .epsilon., the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop. With a pulse with longer than .epsilon. applied to the clock input, the P-type flip-flop appears transparent similar to a latch.

摘要翻译： P型触发器，其选择性地根据其时钟信号输入在D型触发器模式或锁存模式中起作用。 P型触发器具有在其时钟输入的前沿跟随其数据输入的输出改变状态，然后输出不改变周期ε的状态，然后输出改变状态以匹配其之后的数据输入 如果在其时钟输入处接收到具有大于ε的周期的信号的周期ε。 通过在时钟输入端施加的脉冲具有小于ε的宽度，P型触发器的边缘敏感功能类似于D型触发器。 使用长于ε的脉冲施加到时钟输入，P型触发器似乎与锁存器相似。