公开(公告)号：US20230162697A1

公开(公告)日：2023-05-25

申请号：US18083282

申请日：2022-12-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi UMEZAKI

IPC: G09G3/36 ,  G09G3/20 ,  H03K3/356 ,  H03K5/15 ,  G11C19/28

CPC classification number: G09G3/3674 ,  G09G3/3688 ,  G09G3/20 ,  H03K3/356026 ,  H03K5/15066 ,  H03K5/15093 ,  G11C19/287 ,  G11C19/28 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  H03K4/026

Abstract: A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

公开(公告)号：US09871503B2

公开(公告)日：2018-01-16

申请号：US15665070

申请日：2017-07-31

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuyuki Nakanishi

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/356121 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356026 ,  H03K3/35606

Abstract: A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

公开(公告)号：US20170201240A1

公开(公告)日：2017-07-13

申请号：US15397822

申请日：2017-01-04

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Pan Dou XUE ,  Guang Tao FENG ,  Bu Xin ZHANG ,  Hui Hui GU

IPC: H03K3/3562 ,  H03K3/013

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356026 ,  H03K19/096

Abstract: The present disclosure provides D flip-flops and signal driving methods using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit configured to input a first clock signal, a first data signal, a second data signal and a third data signal and generate a clock pulse signal. The clock pulse signal responds a rising-edge and a falling-edge of the first clock signal. The pulse clock signal is a pulse signal when the first data signal is opposite to the second data signal. The D flip-flop also includes a latching circuit configured to sample and transfer the first data signal and a data signal opposite to the first data signal to be used as the second signal and a fourth data signal respectively when the clock signal is at the high level.

公开(公告)号：US20170039976A1

公开(公告)日：2017-02-09

申请号：US15300000

申请日：2016-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: G09G3/36 ,  G11C19/28 ,  H03K3/356

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0404 ,  G09G2300/0413 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28 ,  H03K3/356026

Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Abstract translation: 在像素部分的左侧和右侧设置两个包括移位寄存器和包括单导电型晶体管的解复用器的栅极驱动器。 栅极线在每M行中交替连接到左侧和右侧栅极驱动器。 移位寄存器包括串联连接的k个第一单元电路。 解复用器包括k个第二单位电路，其中每个电路从第一单元电路输入信号，并且连接M个栅极线。 第二单元电路选择在M个栅极线之间输出来自第一单位电路的输入信号的一个或多个布线，并将来自第一单元电路的信号输出到所选择的布线。 由于门信号可以从一级移位寄存器的输出输出到M条栅极线，所以移位寄存器的宽度可以变窄。

公开(公告)号：US09478187B2

公开(公告)日：2016-10-25

申请号：US14714473

申请日：2015-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki Miyake ,  Kouhei Toyotaka

IPC: H03K3/00 ,  G06F1/04 ,  G09G3/36 ,  H03K3/356 ,  G09G5/18 ,  G09G3/32

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0404 ,  G09G2300/0413 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28 ,  H03K3/356026

Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

公开(公告)号：US20160233867A1

公开(公告)日：2016-08-11

申请号：US15132824

申请日：2016-04-19

Applicant: SOCIONEXT INC.

Inventor： Tetsuro TAMURA

IPC: H03K23/52 ,  H03M9/00 ,  H03K21/02 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K23/52 ,  H03K3/037 ,  H03K3/0372 ,  H03K3/356026 ,  H03K19/21 ,  H03K21/026 ,  H03K21/12 ,  H03K23/54 ,  H03M9/00

Abstract: A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.

Abstract translation: 在时钟信号的上升沿驱动的多个锁存电路和在时钟信号的下降沿被驱动的多个锁存电路被交替连接，并且发电电路基于输出电平的组合产生具有不同相位的多个分频时钟信号 的多个锁存电路。

公开(公告)号：US08659337B2

公开(公告)日：2014-02-25

申请号：US13188364

申请日：2011-07-21

Applicant: Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

Inventor： Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

公开(公告)号：US20130154374A1

公开(公告)日：2013-06-20

申请号：US13819400

申请日：2011-08-31

Applicant: Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

Inventor： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

IPC: H02J4/00

CPC classification number: H02J4/00 ,  H03K3/356008 ,  H03K3/356026 ,  H03K19/01714 ,  H03K19/01735 ,  Y10T307/50

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.

Abstract translation: 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以提高自举式信号处理电路的可靠性。

公开(公告)号：US20130063292A1

公开(公告)日：2013-03-14

申请号：US13423061

申请日：2012-03-16

Applicant: Bernard Ginetti

Inventor： Bernard Ginetti

IPC: H03M1/66

CPC classification number: H03K3/356026 ,  H03K5/151 ,  H03K2005/00136

Abstract: The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.

Abstract translation: 本公开提供了使用基于NMOS场效应晶体管的缓冲器来缓冲一对互补数字信号并输出​​一对等效的快速上升和快速下降互补信号的技术，以同时驱动单元电池的差分PMOS晶体管， 输出电流转向DAC的模拟信号。 因此，DAC包括锁存电路和单元电路。 锁存电路包括基于NMOS场效应晶体管的缓冲器，并能够接收第一数字信号和时钟信号，并根据时钟信号通过基于NMOS场效应晶体管的缓冲器输出第二数字信号。 第二数字信号与第一数字信号相关联。 耦合到锁存电路的单元电路接收第二数字信号并输出​​表示第一数字信号的模拟信号。

公开(公告)号：US5506519A

公开(公告)日：1996-04-09

申请号：US253795

申请日：1994-06-03

Applicant: Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

Inventor： Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

IPC: H03K19/0948 ,  H03K3/356 ,  H03K19/00 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K19/0019 ,  H03K19/1738 ,  H03K3/356026 ,  H03K3/356121

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract translation: 无论逻辑信号输入到门的输出还是从门输出，节能逻辑门电路设计为时钟源提供基本恒定的负载。 门提供两个互补输出，并利用交叉耦合晶体管确保在逻辑输入无效后，输出保持有效（互补）。 两个块，每个具有耦合到时钟源并执行互补逻辑功能的节点，与用于对门的输出再充电的二极管相结合，将恒定负载呈现给时钟源。