公开(公告)号：US06746953B2

公开(公告)日：2004-06-08

申请号：US09925765

申请日：2001-08-09

Applicant: Alan H. Kramer ,  Danielle A. Thomas

Inventor： Alan H. Kramer ,  Danielle A. Thomas

IPC: H01L214763

CPC classification number: H01L23/544 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2224/05599

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

Abstract translation: 用于总线导体的金属抽头形成在总线通孔区域中的衬底的有源侧上的一个或多个金属化层内的有源层内。 对准标记形成在相同的金属层中，在同一区域。 然后从基板的背面盲槽蚀刻槽，暴露金属丝锥和对准标记。 使用氧化物或氮化物硬掩模将槽蚀刻到具有显着倾斜的侧壁的衬底的背侧表面中，允许金属在背面上沉积和图案化。 衬底的背面上的绝缘层和沉积的金属可能需要盲目蚀刻以暴露对准标记（如果有的话），而是利用暴露的对准标记的前后对准精度可以允许金属片的两个更小的设计规则 以及由金属层形成的背面互连。 背面接触焊盘也可以由金属层形成。 经由槽的背面总线可以蚀刻在管芯的主体中，靠近中心区域或沿着管芯边界以形成共用的背面总线通孔，其中槽的相对侧上的金属接头连接到不同管芯上的背面接触件 骰子沿边界的分离。 背面总线有利于传感器设备，为传感器电路在活动侧留下更多空间，并简化封装，限制垫片设计和形成可堆叠集成电路。

公开(公告)号：US06618084B1

公开(公告)日：2003-09-09

申请号：US08964763

申请日：1997-11-05

Applicant: Roberto Rambaldi ,  Marco Tartagni ,  Alan H. Kramer

Inventor： Roberto Rambaldi ,  Marco Tartagni ,  Alan H. Kramer

IPC: H04N314

CPC classification number: H04N5/367 ,  H04N5/374

Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well. The disclosed sensor also identifies pixels that were initially acceptable but later became defective. The newly defective pixels so identified may then be masked to thereby increase the CMOS detector lifetime.

公开(公告)号：US5506519A

公开(公告)日：1996-04-09

申请号：US253795

申请日：1994-06-03

Applicant: Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

Inventor： Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

IPC: H03K19/0948 ,  H03K3/356 ,  H03K19/00 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K19/0019 ,  H03K19/1738 ,  H03K3/356026 ,  H03K3/356121

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract translation: 无论逻辑信号输入到门的输出还是从门输出，节能逻辑门电路设计为时钟源提供基本恒定的负载。 门提供两个互补输出，并利用交叉耦合晶体管确保在逻辑输入无效后，输出保持有效（互补）。 两个块，每个具有耦合到时钟源并执行互补逻辑功能的节点，与用于对门的输出再充电的二极管相结合，将恒定负载呈现给时钟源。

公开(公告)号：US06300670B1

公开(公告)日：2001-10-09

申请号：US09360836

申请日：1999-07-26

Applicant: Alan H. Kramer ,  Danielle A. Thomas

Inventor： Alan H. Kramer ,  Danielle A. Thomas

IPC: H01L2940

CPC classification number: H01L23/544 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2224/05599

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

Abstract translation: 用于总线导体的金属抽头形成在总线通孔区域中的衬底的有源侧上的一个或多个金属化层内的有源层内。 对准标记形成在相同的金属层中，在同一区域。 然后从基板的背面盲槽蚀刻槽，暴露金属丝锥和对准标记。 使用氧化物或氮化物硬掩模将槽蚀刻到具有显着倾斜的侧壁的衬底的背侧表面中，允许金属在背面上沉积和图案化。 衬底的背面上的绝缘层和沉积的金属可能需要盲目蚀刻以暴露对准标记（如果有的话），而是利用暴露的对准标记的前后对准精度可以允许金属片的两个更小的设计规则 以及由金属层形成的背面互连。 背面接触焊盘也可以由金属层形成。 经由槽的背面总线可以蚀刻在管芯的主体中，靠近中心区域或沿着管芯边界以形成共用的背面总线通孔，其中槽的相对侧上的金属接头连接到不同管芯上的背面接触件 骰子沿边界的分离。 背面总线有利于传感器设备，为传感器电路在活动侧留下更多空间，并简化封装，限制垫片设计和形成可堆叠集成电路。

公开(公告)号：US5422582A

公开(公告)日：1995-06-06

申请号：US175709

申请日：1993-12-30

Applicant: Steven C. Avery ,  Alexander G. Dickinson ,  Thaddeus J. Gabara ,  Alan H. Kramer

Inventor： Steven C. Avery ,  Alexander G. Dickinson ,  Thaddeus J. Gabara ,  Alan H. Kramer

IPC: H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0948 ,  H03K19/096

CPC classification number: H03K19/0019 ,  H03K19/0963

Abstract: CMOS logic circuitry powered by the clock signals wherein the addition of strategically placed diodes enables the circuits to behave in an adiabatic-like fashion.

Abstract translation: CMOS逻辑电路由时钟信号供电，其中添加了策略性放置的二极管使电路能够以绝热状态运行。

公开(公告)号：US07535502B2

公开(公告)日：2009-05-19

申请号：US10613830

申请日：2003-07-03

Applicant: Roberto Rambaldi ,  Marco Tartagni ,  Alan H. Kramer

Inventor： Roberto Rambaldi ,  Marco Tartagni ,  Alan H. Kramer

IPC: H04N9/64

CPC classification number: H04N5/367 ,  H04N5/374

Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well. The disclosed sensor also identifies pixels that were initially acceptable but later became defective. The newly defective pixels so identified may then be masked to thereby increase the CMOS detector lifetime.

Abstract translation: 公开了一种容错CMOS图像传感器，其包括用于识别缺陷像素并在图像生成期间对其进行掩蔽的电路。 在一个示例中，掩蔽可以包括用周围的非故障像素的输出的平均值代替给定像素的输出。 因此，虽然图像传感器可以被制造成具有若干数量的有缺陷的像素，但由这种传感器产生的图像将不会有不期望的明亮或暗点。 所公开的传感器包括（a）能够提供指示一个或多个像素中的每一个已被暴露的辐射量的输出的一个或多个像素（有源或无源） 和（b）一个或多个电路元件，其电耦合到所述一个或多个像素并且被配置为识别和校正所述CMOS成像器中的有缺陷的像素。 每一个像素都包括在阱中形成的光电二极管扩散器和也形成在阱中的电源或接地的抽头。 所公开的传感器还识别最初可接受但后来变得有缺陷的像素。 然后可以掩蔽如此识别的新缺陷像素，从而增加CMOS检测器的寿命。

公开(公告)号：US06504572B2

公开(公告)日：2003-01-07

申请号：US08964762

申请日：1997-11-05

Applicant: Alan H. Kramer ,  Roberto Rambaldi ,  Marco Tartagni

Inventor： Alan H. Kramer ,  Roberto Rambaldi ,  Marco Tartagni

IPC: H04N314

CPC classification number: H04N5/367 ,  H04N5/374

Abstract: Disclosed is a CMOS image sensor that includes circuitry for identifying defective pixels, particularly pixels having leaky access switches. The leaky access switches allow charge to escape from the pixel over a row or column line in a pixel array, thereby corrupting the outputs of an entire row or column of pixels. A disclosed test involves (a) electronically setting a defined charge in a selected pixel of the CMOS imager; (b) reading the output of the selected pixel; and (c) comparing the output of the selected pixel to an expected value based upon the defined charge set in the selected pixels. If the output significantly deviates from the expected value, then the selected pixel is identified as having a leaky access switch. Preferably, a newly fabricated sensor is first tested as described. If such leaky access switch is discovered, the imager is discarded without incurring further manufacturing cost. If, on the other hand, the imager is not found to contain a leaky access switch, it may packaged and then subjected to an optical test.

Abstract translation: 公开了一种CMOS图像传感器，其包括用于识别缺陷像素的电路，特别是具有泄漏接入开关的像素。 泄漏的访问开关允许电荷从像素阵列中的行或列线上的像素逸出，从而破坏整个像素行或列的输出。 公开的测试涉及（a）在CMOS成像器的选定像素中电子地设定定义的电荷; （b）读取所选像素的输出; 以及（c）基于所选择的像素中设定的定义的电荷，将所选像素的输出与预期值进行比较。 如果输出显着偏离预期值，则所选择的像素被识别为具有泄漏接入开关。 优选地，如上所述首先测试新制造的传感器。 如果发现这种泄漏接入交换机，则丢弃该成像器而不会产生进一步的制造成本。 另一方面，如果没有发现成像器含有泄漏接入开关，则可以对其进行打包，然后进行光学测试。

公开(公告)号：US6067025A

公开(公告)日：2000-05-23

申请号：US984007

申请日：1997-12-03

Applicant: Anthony M. Chiu ,  Alan H. Kramer

Inventor： Anthony M. Chiu ,  Alan H. Kramer

IPC: H01L23/544 ,  H01L23/58 ,  G08B21/00

CPC classification number: H01L22/34 ,  H01L23/58 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/859 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10T29/49037

Abstract: An apparatus and method for controlling the height of packaging above an integrated circuit package (30) comprising, a substrate (12), a silicon chip (16) and a signal wire (20), one or more height detection wires (32) extending above the top surface (26) of the silicon chip (16) and the signal wire (20) and a detector electrically connected to the height detection wire (32), wherein the height detection wire (32) and the detector form an electric circuit that is affected when a polisher of encapsulant (40) is in proximity to the height detection wire (32), is disclosed.

Abstract translation: 一种用于控制集成电路封装（30）上方的封装高度的装置和方法，包括：衬底（12），硅芯片（16）和信号线（20），一个或多个高度检测线（32）延伸 在硅芯片（16）的顶表面（26）和信号线（20）之上，以及电连接到高度检测线（32）的检测器，其中高度检测线（32）和检测器形成电路 公开了当密封剂（40）的抛光机靠近高度检测线（32）时受到影响。

公开(公告)号：US5559463A

公开(公告)日：1996-09-24

申请号：US229258

申请日：1994-04-18

Applicant: John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

Inventor： John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

IPC: H03K3/354 ,  H03K17/0416 ,  H03K19/00 ,  H03K19/0948 ,  H03K5/12 ,  H03K5/18

CPC classification number: H03K17/04163 ,  H03K19/0019 ,  H03K3/354

Abstract: High-efficiency clock generator circuits having single or complementary outputs for driving capacitive loads. The clock generator has therein at least one pair of complementary FET switches, coupled between the output of the generator and power supply rails, and an inductor. The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.

Abstract translation: 具有用于驱动容性负载的单个或互补输出的高效率时钟发生器电路。 时钟发生器在其中具有耦合在发生器的输出端和电源轨道之间的至少一对互补FET开关和电感器。 发电机以大约等于电感器的谐振频率与负载电容相结合的频率工作。 通常存储在负载中并像在常规时钟发生器中一样消耗在FET中的能量被存储在电感器中并返回到负载以供重新使用。

公开(公告)号：US5264734A

公开(公告)日：1993-11-23

申请号：US885529

申请日：1992-05-19

Applicant: Mark A. Holler ,  Simon M. Tam ,  Alan H. Kramer

Inventor： Mark A. Holler ,  Simon M. Tam ,  Alan H. Kramer

IPC: G06F15/18 ,  G06G7/60 ,  G06N3/063 ,  G06N99/00 ,  H03K19/173 ,  H03K19/177 ,  H03K19/08

CPC classification number: G06N3/063 ,  G06N3/0635

Abstract: A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one of a pair of complementary input voltages. The floating gate devices also have complementary threshold voltages such that packets of charge are produced from the synapse cells that are proportional to the difference between the input and voltage threshold. The charge packets are accumulated by the pairs of column lines in the array.

Abstract translation: 公开了一种差分计算神经网络，其具有沿着行和列线对的行和列排列的突触细胞阵列。 这些单元包括一对浮置栅极器件，它们的控制栅极耦合以接收一对互补输入电压中的一个。 浮置栅极器件还具有互补的阈值电压，使得从与输入和电压阈值之间的差成比例的突触电池产生电荷分组。 电荷分组由阵列中的列线对累积。