公开(公告)号：US06300670B1

公开(公告)日：2001-10-09

申请号：US09360836

申请日：1999-07-26

Applicant: Alan H. Kramer ,  Danielle A. Thomas

Inventor： Alan H. Kramer ,  Danielle A. Thomas

IPC: H01L2940

CPC classification number: H01L23/544 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2224/05599

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

Abstract translation: 用于总线导体的金属抽头形成在总线通孔区域中的衬底的有源侧上的一个或多个金属化层内的有源层内。 对准标记形成在相同的金属层中，在同一区域。 然后从基板的背面盲槽蚀刻槽，暴露金属丝锥和对准标记。 使用氧化物或氮化物硬掩模将槽蚀刻到具有显着倾斜的侧壁的衬底的背侧表面中，允许金属在背面上沉积和图案化。 衬底的背面上的绝缘层和沉积的金属可能需要盲目蚀刻以暴露对准标记（如果有的话），而是利用暴露的对准标记的前后对准精度可以允许金属片的两个更小的设计规则 以及由金属层形成的背面互连。 背面接触焊盘也可以由金属层形成。 经由槽的背面总线可以蚀刻在管芯的主体中，靠近中心区域或沿着管芯边界以形成共用的背面总线通孔，其中槽的相对侧上的金属接头连接到不同管芯上的背面接触件 骰子沿边界的分离。 背面总线有利于传感器设备，为传感器电路在活动侧留下更多空间，并简化封装，限制垫片设计和形成可堆叠集成电路。

公开(公告)号：US06746953B2

公开(公告)日：2004-06-08

申请号：US09925765

申请日：2001-08-09

Applicant: Alan H. Kramer ,  Danielle A. Thomas

Inventor： Alan H. Kramer ,  Danielle A. Thomas

IPC: H01L214763

CPC classification number: H01L23/544 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2224/05599

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

Abstract translation: 用于总线导体的金属抽头形成在总线通孔区域中的衬底的有源侧上的一个或多个金属化层内的有源层内。 对准标记形成在相同的金属层中，在同一区域。 然后从基板的背面盲槽蚀刻槽，暴露金属丝锥和对准标记。 使用氧化物或氮化物硬掩模将槽蚀刻到具有显着倾斜的侧壁的衬底的背侧表面中，允许金属在背面上沉积和图案化。 衬底的背面上的绝缘层和沉积的金属可能需要盲目蚀刻以暴露对准标记（如果有的话），而是利用暴露的对准标记的前后对准精度可以允许金属片的两个更小的设计规则 以及由金属层形成的背面互连。 背面接触焊盘也可以由金属层形成。 经由槽的背面总线可以蚀刻在管芯的主体中，靠近中心区域或沿着管芯边界以形成共用的背面总线通孔，其中槽的相对侧上的金属接头连接到不同管芯上的背面接触件 骰子沿边界的分离。 背面总线有利于传感器设备，为传感器电路在活动侧留下更多空间，并简化封装，限制垫片设计和形成可堆叠集成电路。

公开(公告)号：US07339204B2

公开(公告)日：2008-03-04

申请号：US09969366

申请日：2001-10-01

Applicant: Danielle A. Thomas

Inventor： Danielle A. Thomas

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts. By forming a shared contact opening spanning two dice, the backside contact is formed around the die edge and the backside surface area necessary for the contact opening is minimized. The backside contact allows direct placement of the integrated circuit die on contacts within the packaging, such as a ball grid array, eliminating the need for wire bonds. The need for a pad etch through passivation material overlying active devices on the front side of the die is also eliminated, and no mask levels are added for the devices formed on the front side.

Abstract translation: 接触在模具的边缘处的衬底的有源区域内形成，优选地在衬底的有源区域中的第一金属化水平范围内。 然后将具有倾斜侧壁的开口蚀刻到衬底的背面，暴露一部分有源区接触。 在开口侧壁上形成互连件，以将有源区域接触件与衬底的背面上的管芯接触焊盘相连接。 活性区域接触件优选地跨越两个管芯之间的边界，其中开口优选地蚀刻跨越边界，以允许在开口的相对侧壁上的互连，以使每一个与不同管芯内的有源区接触部接触，将有源区接触件连接到管芯接触 垫在不同的骰子。 然后将骰子沿着边界通过有源区接触分离，该有源区接触成为两个单独的有源区触点。 通过形成横跨两个骰子的共享接触开口，在模具边缘周围形成背面接触，并使接触开口所需的背面面积最小化。 背面接触允许将集成电路管芯直接放置在封装内的触点上，例如球栅阵列，从而不需要引线键合。 还消除了通过覆盖裸片前侧上的有源器件的钝化材料进行衬垫蚀刻的需要，并且不对前侧形成的器件添加掩模级别。

公开(公告)号：US07323114B2

公开(公告)日：2008-01-29

申请号：US11248784

申请日：2005-10-12

Applicant: Anthony M. Chiu ,  Danielle A. Thomas

Inventor： Anthony M. Chiu ,  Danielle A. Thomas

IPC: B29D11/00

CPC classification number: G11B7/1372 ,  G02B6/4214 ,  G02B6/43 ,  G11B7/123

Abstract: A large diameter glass wafer is pattern-etched to provide a plurality of elongated lens elements arranged side-by-side, the etching leaving small rods in place to keep the lens elements connected to the wafer during mirror processing. The etching provides curved surfaces for lenses and flat surfaces for mirrors. The mirrors are formed by selectively depositing reflective material on the flat surfaces. The reflective material may comprise an oxide, nitride, sulfide, or fluoride of a transition metal. The flat surfaces that define the mirrors are disposed at angles to the longitudinal dimension of each lens element. In use in an optical disc system, light from a laser diode is reflected by the mirrors and directed at an optical disc through a first lens. Light returns from the disc on a parallel path through a second lens, passes through the lens element, and is directed at a photodetector. The system may include an elongated base element attached to each lens element. Pattern-etching of a second glass wafer provides multiple base elements per wafer. Each base element may include an angled surface on which a reflective material is deposited to form a mirror for reflecting laser light during use in the system.

Abstract translation: 大直径玻璃晶片被图案蚀刻以提供并排设置的多个细长透镜元件，蚀刻将小棒留在适当位置，以在镜面处理期间保持透镜元件连接到晶片。 蚀刻为镜子提供弯曲表面和镜子的平坦表面。 反射镜通过在平坦表面上选择性地沉积反射材料而形成。 反射材料可以包含过渡金属的氧化物，氮化物，硫化物或氟化物。 限定反射镜的平坦表面设置成与每个透镜元件的纵向尺寸成角度。 在光盘系统中使用时，来自激光二极管的光被反射镜反射并通过第一透镜指向光盘。 光从平行路径通过第二透镜从光盘返回，穿过透镜元件，并被引导到光电检测器。 该系统可以包括附接到每个透镜元件的细长基部元件。 第二玻璃晶片的图案蚀刻为每个晶片提供多个基底元件。 每个基本元件可以包括成角度的表面，反射材料沉积在该倾斜表面上以形成用于在系统中使用期间反射激光的反射镜。

公开(公告)号：US06559488B1

公开(公告)日：2003-05-06

申请号：US09838909

申请日：2001-04-20

Applicant: Danielle A. Thomas ,  Gilles E. Thomas

Inventor： Danielle A. Thomas ,  Gilles E. Thomas

IPC: H01L2980

CPC classification number: H01L27/1462 ,  H01L27/14609

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response.

Abstract translation: 光电检测器集成在具有双极晶体管的单个半导体芯片上，该晶体管包括高速多晶硅垂直NPN晶体管。 光检测器包括用作抗反射膜的氮化硅层。 氮化硅层和其相对侧上的氧化物层将多晶硅发射极的边缘与下面的晶体管区域绝缘，从而最小化NPN晶体管的发射极之间的寄生电容并实现高频率响应。

公开(公告)号：US06478976B1

公开(公告)日：2002-11-12

申请号：US09224815

申请日：1998-12-30

Applicant: Arnaud Yves Lepert ,  Danielle A. Thomas ,  Antonio A. Do-Bento-Vieira

Inventor： Arnaud Yves Lepert ,  Danielle A. Thomas ,  Antonio A. Do-Bento-Vieira

IPC: H01L2100

CPC classification number: G06K9/00053

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract translation: 一种用于在导电层和用于消散静电荷的焊盘之间产生接触的结构和方法，包括以下步骤：在衬底上的导电板之间和之上形成衬垫和复合绝缘层，其中绝缘层隔离并保护导电 板和垫从损坏中，绝缘层包括导电层下面的电介质区域。 在导电层的至少一部分上形成钝化层，并且在至少一部分钝化层上形成光刻胶。 通过钝化和绝缘层蚀刻开口，其中光致抗蚀剂和导电层用作掩模。 最后，导电材料沉积在开口中以在焊盘和导电层之间形成电接触。

公开(公告)号：US06448103B1

公开(公告)日：2002-09-10

申请号：US09870259

申请日：2001-05-30

Applicant: Danielle A. Thomas

Inventor： Danielle A. Thomas

IPC: H01L2100

CPC classification number: H03H3/0072 ,  H03H3/0077 ,  H03H9/2457

Abstract: A cantilevered beam is formed over a cavity to an accurate length by isotropically etching a fast-etching material, such as hydrogen silisquioxane, out of the cavity. The cavity is initially defined within a slow-etching material. The selectivity of the etch rates of the material within the cavity relative to the material defining the walls of the cavity permits accurate control of the length of the free end of the cantilevered beam. The resonant frequency of the cantilevered beam can be tuned to a narrow predetermined range by laser trimming.

Abstract translation: 通过将诸如氢硅倍半氧烷之类的快速蚀刻材料各向异性地蚀刻到空腔内，在空腔上形成悬臂梁至精确的长度。 最初在缓蚀刻材料内限定空腔。 相对于限定空腔壁的材料，空腔内的材料的蚀刻速率的选择性允许准确地控制悬臂梁的自由端的长度。 悬臂梁的谐振频率可以通过激光修整调整到窄的预定范围。

公开(公告)号：US06423995B1

公开(公告)日：2002-07-23

申请号：US09360839

申请日：1999-07-26

Applicant: Danielle A. Thomas

Inventor： Danielle A. Thomas

IPC: H01L27108

CPC classification number: H01L23/642 ,  G06K9/00053 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines. Tungsten is a suitable conductive material, for which existing processes may be substituted in place of aluminum metallization processes.

Abstract translation: 在需要物理接触并且过度压力可能无意中施加到传感器表面的电容式传感器电路中，即使钝化完整性保持完整，铝也不能很好地提供“划伤”保护并且可能分层，导致电路故障。 因为单独的硬钝化层提供不足的耐擦伤性，所以至少电容电极和优选地，在基片的表面和有源区之间的电容电极区域内的传感器电路内的所有金属化水平由具有硬度的导电材料形成 大于铝。 所选择的导电材料优选具有至少与任何使用的层间电介质或钝化材料的最低硬度一样大的硬度。 所选择的导电材料用于表面和有源区域之间的每个金属化水平，包括触点和通孔，着陆焊盘，互连，电容电极和静电放电保护线。 钨是一种合适的导电材料，现有工艺可以代替铝金属化工艺。

公开(公告)号：US06326227B1

公开(公告)日：2001-12-04

申请号：US09223707

申请日：1998-12-30

Applicant: Danielle A. Thomas ,  Ming Fang

Inventor： Danielle A. Thomas ,  Ming Fang

IPC: H01L2100

CPC classification number: G06K9/00053

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the topographic discharge grid fills at least a portion of the gap between the plates over the dielectric layer and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract translation: 一种用于耗散电荷的结构和方法，包括设置在传感器电路的电容器板之上的下面的介电层，在相邻的板之间保形地形成间隙，并且在下面的介电层上方形成地形放电栅格，并且其中，地形放电栅格填充至少一部分 电介质层之间的间隙，并在集成电路的表面扩散静电电荷。

公开(公告)号：US20120091517A1

公开(公告)日：2012-04-19

申请号：US13232171

申请日：2011-09-14

Applicant: Danielle A. Thomas

Inventor： Danielle A. Thomas

IPC: H01L27/06

CPC classification number: H01L23/642 ,  G06K9/00053 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract translation: 在需要物理接触并且过度压力可能无意中施加到传感器表面的电容式传感器电路中，即使钝化完整性保持完整，铝也不能很好地提供“划伤”保护并且可能分层，导致电路故障。 因为单独的硬钝化层提供不足的耐擦伤性，所以至少电容电极和优选地，在基片的表面和有源区之间的电容电极区域内的传感器电路内的所有金属化水平由具有硬度的导电材料形成 大于铝，并且至少与所采用的任何层间电介质或钝化材料的最低硬度一样大。