公开(公告)号：US06762629B2

公开(公告)日：2004-07-13

申请号：US10206610

申请日：2002-07-26

Applicant: Simon M. Tam ,  Stefan Rusu

Inventor： Simon M. Tam ,  Stefan Rusu

IPC: H03B1900

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3296 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18 ,  H03L7/22 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.

Abstract translation: 一种用于在处理器中动态地改变时钟频率以适应VCC电压变化的方法和装置。 一个实施例的方法包括对多个位置处的电源电压进行采样。 所述电源电压的值被传送到时钟发生器。 响应于对电源电压的采样值的评估，调整从时钟发生器产生的时钟信号的时钟频率。

公开(公告)号：US06201448B1

公开(公告)日：2001-03-13

申请号：US09473925

申请日：1999-12-28

Applicant: Simon M. Tam ,  Stefan Rusu

Inventor： Simon M. Tam ,  Stefan Rusu

IPC: H03L706

CPC classification number: H03L7/06 ,  G06F1/10 ,  H03L7/081

Abstract: An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.

Abstract translation: 一个片上时钟发生器。 对于本发明的一个方面，片上时钟发生器包括锁相环（PLL）电路，其具有耦合以接收外部时钟信号的第一输入和耦合以提供待使用的时钟信号的输出 集成电路的正常工作模式。 片上时钟发生器还包括具有耦合以接收片上时钟信号的输入的本地时钟发生器电路，以及耦合以将本地PLL反馈时钟信号提供给PLL的第二输入的输出。

公开(公告)号：US5087826A

公开(公告)日：1992-02-11

申请号：US635231

申请日：1990-12-28

Applicant: Mark A. Holler ,  Simon M. Tam

Inventor： Mark A. Holler ,  Simon M. Tam

IPC: G06F15/18 ,  G06G7/60 ,  G06N3/04 ,  G06N99/00

CPC classification number: G06N3/0445

Abstract: A multi-layer electrically trainable analog neural network employing multiplexed output neurons having inputs organized into two groups, external and recurrent (i.e., feedback). Each layer of the network comprises a matrix of synapse cells which implement a matrix multiplication between an input vector and a weight matrix. In normal operation, an external input vector coupled to the first synaptic array generates a Sigmoid response at the output of a set of neurons. This output is then fed back to the next and subsequent layers of the network as a recurrent input vector. The output of second layer processing is generated by the same neurons used in first layer processing. Thus, the neural network of the present invention can handle N-layer operation by using recurrent connections and a single set of multiplexed output neurons.

Abstract translation: 一种多层电可训练的模拟神经网络，其使用具有组合成两组的输入的多路复用输出神经元，外部和复发（即，反馈）。 网络的每个层包括突变单元的矩阵，其实现输入向量和权重矩阵之间的矩阵乘法。 在正常操作中，耦合到第一突触阵列的外部输入向量在一组神经元的输出处产生S形反应。 然后将该输出作为反复输入向量反馈到网络的下一层和后续层。 第二层处理的输出由第一层处理中使用的相同神经元产生。 因此，本发明的神经网络可以通过使用循环连接和单组多路复用输出神经元来处理N层操作。

公开(公告)号：US5075869A

公开(公告)日：1991-12-24

申请号：US557555

申请日：1990-06-24

Applicant: Mark A. Holler ,  Hernan A. Castro ,  Simon M. Tam

Inventor： Mark A. Holler ,  Hernan A. Castro ,  Simon M. Tam

IPC: G06N3/063

CPC classification number: G06N3/0635

Abstract: An analog neural network is described which provides a means for reducing the sensitivity of the network to temperature and power supply variations. A first circuit is utilized for generating a signal which exhibits a dependence on temperature corresponding to the variation normally experienced by the network in response to a change in temperature. A second circuit is employed to generate another signal which exhibits a similar dependence, except on power supply variations. By coupling these signals as inputs to the neural network the sensitivity of the network to temperature and power supply fluctuations is essentially nulified.

Abstract translation: 描述了一种模拟神经网络，其提供了降低网络对温度和电源变化的灵敏度的手段。 第一电路用于产生对应于温度变化通常由网络经历的变化的温度的依赖性的信号。 除了电源变化之外，使用第二电路产生表现出相似依赖性的另一信号。 通过将这些信号作为输入耦合到神经网络，网络对温度和电源波动的敏感度基本上是nulified。

公开(公告)号：US4956564A

公开(公告)日：1990-09-11

申请号：US379933

申请日：1989-07-13

Applicant: Mark A. Holler ,  Simon M. Tam ,  Hernan A. Castro

Inventor： Mark A. Holler ,  Simon M. Tam ,  Hernan A. Castro

IPC: G11C11/54 ,  G06N3/063 ,  G11C15/04

CPC classification number: G06N3/0635 ,  G06N3/063 ,  G11C15/046

Abstract: The present invention covers a synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's control gate is coupled to an input line and its drain is coupled to an output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current, and therefore the resulting discharge, is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.

Abstract translation: 本发明涵盖用于在输入电压线和具有相关电容的输出求和线之间提供加权连接的突触电池。 关联网络中的输入和输出线之间的连接是使用一个或多个提供兴奋性和抑制性连接两者的浮栅晶体管进行的。 如所配置的，每个晶体管的控制栅极耦合到输入线，并且其漏极耦合到输出求和线。 晶体管的浮置栅极用于存储对应于神经连接的强度或重量的电荷。 当具有一定持续时间的二进制电压脉冲被施加到浮栅晶体管的控制栅极时，产生用于放电与输出求和线相关联的电容的电流。 电流，因此产生的放电与存储在浮栅器件上的电荷和输入脉冲的持续时间成正比。

公开(公告)号：US4814286A

公开(公告)日：1989-03-21

申请号：US192296

申请日：1988-05-09

Applicant: Simon M. Tam

Inventor： Simon M. Tam

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/94 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7885

Abstract: An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the folating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.

Abstract translation: 一种电可编程和电可擦除浮动存储器件，其包括一体形成的选择装置。 在n沟道实施例中，在控制栅极下方的漏区附近形成一个硼区，并在叶栅下方略微延伸。 该区域使用由各向异性蚀刻步骤限定的间隔来形成。 除了提供增强的编程之外，该区域还防止在发生过度擦除时的传导，即当擦除导致电池耗尽时。

公开(公告)号：US06908227B2

公开(公告)日：2005-06-21

申请号：US10227125

申请日：2002-08-23

Applicant: Stefan Rusu ,  Simon M. Tam

Inventor： Stefan Rusu ,  Simon M. Tam

IPC: G01K1/02 ,  G01K7/42 ,  G06F1/20 ,  G01K13/00 ,  G06F1/32

CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K7/42 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

Abstract translation: 描述了一种用于管理具有多核微处理器的集成电路的温度的装置。 具体来说，热传感器放置在每个微处理器核心的潜在热点。 热管理单元监视热传感器。 如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

公开(公告)号：US06788156B2

公开(公告)日：2004-09-07

申请号：US10456660

申请日：2003-06-06

Applicant: Simon M. Tam ,  Stefan Rusu

Inventor： Simon M. Tam ,  Stefan Rusu

IPC: H03B2800

CPC classification number: G06F1/324 ,  G06F1/3203 ,  H03L7/06 ,  H03L7/0805 ,  Y02D10/126

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract translation: 一种在处理器中动态地改变时钟频率的方法。 一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。 可调时钟发生器与锁相环锁定。 可调时钟发生器代替时钟分配网络上的PLL。

公开(公告)号：US5268320A

公开(公告)日：1993-12-07

申请号：US865451

申请日：1992-04-09

Applicant: Mark A. Holler ,  Simon M. Tam

Inventor： Mark A. Holler ,  Simon M. Tam

IPC: G06N3/063 ,  G11C27/00 ,  H01L29/788 ,  H01L21/265 ,  H01L21/76

CPC classification number: G06N3/0635 ,  G11C27/005 ,  H01L29/7887 ,  Y10S438/91

Abstract: A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed.Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.

Abstract translation: 描述了一种用于增加计算输入向量和存储的权重模式之和的乘积的模拟神经网络的精度的方法。 在本发明的一个实施例中，该方法包括通过以某种权重模式编程突触来初始训练网络。 可以使用任何标准学习算法进行训练。 优选地，采用反向传播学习算法。 接下来，网络在升高的温度下烘烤以实现初始训练中先前编程的重量模式的变化。 这种变化是由于网络每个突触中发生的电荷再分配产生的。 烘烤后，网络再次进行补充，以补偿由电荷重新分配引起的变化。 烘焙和再培训步骤可以连续重复，以将神经网络的精度提高到任何所需的水平。

公开(公告)号：US4957877A

公开(公告)日：1990-09-18

申请号：US274420

申请日：1988-11-21

Applicant: Simon M. Tam ,  Stefan K. C. Lai

Inventor： Simon M. Tam ,  Stefan K. C. Lai

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/7883

Abstract: Improved processing which permits the simultaneous fabrication of block erasable flash EPROM cells and individually erasable EEPROM cells. A polysilicon finger extends from the floating gate of the EEPROM cell over a tunnel oxide region. Doped regions are formed under this finger by implanting dopants in alignment with the finger during the implantation of the source and drain regions for the cells and then driving the dopant under the finger. The arsenic dopant used to form the source and drain regions for the cells is used to form the doped regions along with the phosphorus dopant used for the source region of the flash EPROM cells.

Abstract translation: 改进的处理，允许同时制造块可擦除闪存EPROM单元和单独可擦除EEPROM单元。 多晶硅指状物从EEPROM单元的浮动栅极延伸穿过隧道氧化物区域。 通过在用于单元的源极和漏极区域的注入期间注入与手指对准的掺杂剂，然后在手指下驱动掺杂剂，在该手指下方形成掺杂区域。 用于形成用于电池的源极和漏极区域的砷掺杂物用于与用于闪存EPROM单元的源极区域的磷掺杂物一起形成掺杂区域。