公开(公告)号：US6137716A

公开(公告)日：2000-10-24

申请号：US920111

申请日：1997-08-26

Applicant: Thomas R. Wik

Inventor： Thomas R. Wik

IPC: G11C11/406 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/0416 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/412 ,  G11C16/08 ,  G11C7/16 ,  G11C8/14

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements. A first storage element is configured with a first state which is one of a first plurality of states, and a second storage element is configured with a second state which is one of a second, different plurality of states. The sense amplifier is coupled to the selected cell via a bit line and configured to detect the first and second states. Each cell may further include a third storage element configured with a third state which is one of a third plurality of states. In this case, the sense amplifier is also configured to detect the third state. Examples of candidate storage states include charges on a capacitance, conductivities of transistors, resistances between terminals, turn-on voltages of transistors, currents flowing in closed loops, and orientations of magnetized material.

Abstract translation: 一种在每个存储单元中使用多个存储机制的存储器电路。 在一个实施例中，存储器电路包括其中每个单元具有多个存储元件的单元阵列。 至少一个存储元件以与其余存储元件不同的方式执行其功能。 多个存储机制的使用允许存储器单元设计更大的自由度，并且允许在单个存储器单元中同时存储多个状态。 广义地说，本发明考虑了包括地址解码器，单元阵列和读出放大器的存储器核心。 地址解码器被配置为接收地址并且响应地断言所选择的字线。 单元阵列包括耦合到所选字线的选定单元，并且单元阵列中的每个单元包括至少两个存储元件。 第一存储元件配置有作为第一多个状态之一的第一状态，并且第二存储元件被配置为第二状态，其是第二，不同的多个状态之一。 感测放大器经由位线耦合到所选择的单元并被配置为检测第一和第二状态。 每个单元还可以包括配置有第三状态的第三存储元件，该第三状态是第三多个状态之一。 在这种情况下，读出放大器也被配置为检测第三状态。 候选存储状态的示例包括电容的电荷，晶体管的电导率，端子之间的电阻，晶体管的导通电压，在闭环中流动的电流和磁化材料的取向。

公开(公告)号：US5867423A

公开(公告)日：1999-02-02

申请号：US838799

申请日：1997-04-10

Applicant: Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

Inventor： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/112

CPC classification number: G11C11/5692 ,  G11C7/16

Abstract: A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract translation: 根据本发明，通过选择性地设置存储器阵列中的晶体管的阈值电压，能够在存储器单元中存储多于两个逻辑状态的电路和方法。 在一个实施例中，存储电路包括存储晶体管阵列。 每个存储晶体管具有连接到相关读取线的栅极。 当读线被确认时，流经所选择的存储晶体管的电流指示存储的逻辑状态。 通过在制造期间设置每个存储晶体管的阈值电压来分别选择通过每个晶体管的电流。 阵列中的不同晶体管配置有不同的阈值电压，从而表示不同的存储状态。 模数（A / D）转换器耦合到选定的存储晶体管，以便感测电流并确定所表示的状态。 由于每个单元可以表示多于两个存储状态之一，所以存储器电路可以有利地允许将更多数量的位存储在每个存储单元中，从而增加存储密度并降低每位的成本。

公开(公告)号：US5808932A

公开(公告)日：1998-09-15

申请号：US779991

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/41 ,  G11C11/56 ,  G11C11/24

CPC classification number: G11C11/565 ,  G11C7/16

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract translation: 一种能够在存储器单元中存储多于两个逻辑状态的存储器电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由存储在晶体管门上的电荷决定。 通过使能够以离散增量检测电流，可以用存储在存储单元中的电荷来表示多于一位的信息。 额外增量的使用需要更精确的存储和检测电路。 在一个实施例中，存储电路使用反馈来获得更大的逻辑状态检索精度。

公开(公告)号：US06233197B1

公开(公告)日：2001-05-15

申请号：US09524734

申请日：2000-03-14

Applicant: Ghasi R. Agrawal ,  Thomas R. Wik

Inventor： Ghasi R. Agrawal ,  Thomas R. Wik

IPC: G11C800

CPC classification number: G11C7/18 ,  G11C8/16

Abstract: A multi-port semiconductor memory includes first and second data ports and a plurality of memory cells arranged in rows and columns. Each column comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells in that column. The first pair of bit lines cross one another between every N and N+1 of the memory cells the column, where N=2M and M is an integer variable greater than zero. A data inversion circuit is coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M+1)th row address input bit only, as measured from the least significant row address input bit.

Abstract translation: 多端口半导体存储器包括第一和第二数据端口以及以行和列排列的多个存储单元。 每列包括第一和第二对互补位线，其被耦合到该列中的每个存储器单元。 第一对位线在存储单元的每个N和N + 1之间彼此交叉，其中N = 2M，M是大于零的整数变量。 数据反相电路耦合在第一对位线与第一数据端口之间，该第一数据端口根据第一端口的第（M + 1）行地址输入位仅选择性地反转第一对位线， 最低有效行地址输入位。

公开(公告)号：US5987632A

公开(公告)日：1999-11-16

申请号：US852692

申请日：1997-05-07

Applicant: V. Swamy Irrinki ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Thomas R. Wik

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G06F11/00 ,  G11C7/00

CPC classification number: G11C29/72 ,  G11C29/44 ,  G11C29/78 ,  G11C2029/0405

Abstract: A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry. The test suite may then be re-executed, and the device deemed defective if additional errors are found. Rows and columns in the memory array that are prone to failure are thus never enabled. Additionally, the BIST and BISR circuitry provides the ability to verify basic memory functionality and remap failing addresses on each application of power to the device. Test coverage of the memory array is advantageously increased.

Abstract translation: 用于存储器件的测试方法，其中仅在特定最坏情况条件下发生的故障被转换为硬功能故障。 随后通过内置自检（BIST）和内置自修复（BISR）电路检测和重新映射这些位置。 首先，在包含冗余行和列位置的存储器阵列上执行测试套件。 通常，该测试套件在最有可能引起故障的条件下执行。 被确定为故障的行和列位置以及可用的冗余行和列的数量被扫描出存储器设备。 如果有足够的冗余位置，则通过吹动每个相应的熔丝链，永久禁用故障行和列。 当随后将功率应用于存储设备时，BIST将检测具有硬功能故障的行和列，包括永久禁用的列和列。 然后可以通过BISR电路重定向这些位置的访问。 然后可以重新执行测试套件，并且如果发现另外的错误，则该设备被认为是有缺陷的。 因此，永远不会启用内存阵列中容易出现故障的行和列。 此外，BIST和BISR电路提供了验证基本内存功能的能力，并在每次应用设备电源时重新映射失败的地址。 存储器阵列的测试覆盖有利地增加。

公开(公告)号：US5841695A

公开(公告)日：1998-11-24

申请号：US865470

申请日：1997-05-29

Applicant: Thomas R. Wik

Inventor： Thomas R. Wik

IPC: G11C11/406 ,  G11C11/56 ,  G11C16/04 ,  G11C16/02

CPC classification number: G11C16/0416 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/412 ,  G11C16/08 ,  G11C7/16 ,  G11C8/14

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted. The data sense module is coupled to the first and second data lines, and configured to sense the second charge if the third word line is asserted while the second word line is asserted. The data sense module is further configured to sense the third charge by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module is still further configured to detect the first charge by storing a fourth charge on said second gate if the first word line is asserted while the first data line is de-asserted, the first data line is then asserted, and the first word line is then de-asserted at a predetermined time period after the assertion of the first data line. The fourth charge is then sensed by detecting a current through the second transistor if the second word line is de-asserted while the third word line is asserted. The data sense module determines the state represented by the stored charge quantities. Since additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

公开(公告)号：US5903505A

公开(公告)日：1999-05-11

申请号：US858271

申请日：1997-05-19

Applicant: Thomas R. Wik ,  Tuan Phan ,  Thien Trieu

Inventor： Thomas R. Wik ,  Tuan Phan ,  Thien Trieu

IPC: G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/08 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/02 ,  G11C29/50

Abstract: A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value. Driving the write bit line low may be accomplished by repetitively reading the second memory cell. The same effect may alternately be achieved by repetitively writing a logic low value to the second memory cell. By keeping the write bit line at a logic low level during testing of refresh operations, the subthreshold leakage current through the write transistor of the first memory cell may be increased. This accelerates the discharge of the first memory value, and insures testing is performed near worst-case conditions.

Abstract translation: 一种用于测试存储器阵列的刷新操作的方法，其中可将亚阈值泄漏电流设置为接近最坏情况条件。 存储器阵列包括具有配置为存储第一存储器值的第一存储器单元的第一行存储器单元，以及具有被配置为存储第二存储器值的第二存储器单元的第二行存储器单元。 该方法包括将逻辑高值存储到第一存储器单元作为第一存储器值，随后将逻辑低值存储到第二存储器单元作为第二存储器值。 该方法还包括在等于与第一存储器单元相对应的刷新间隔的时间周期内重复驱动以逻辑低电平耦合到第一和第二存储器单元两者的写位线。 另外，该方法包括随后从第一存储器单元读取第一存储器值。 最后，如果第一存储器值仍然等于逻辑高值，则该方法包括指示第一存储器单元正在正常工作，或者如果第一存储器值等于逻辑低值，则指示第一存储器值发生故障。 将写位线驱动为低可以通过重复读取第二存储单元来实现。 可以通过将逻辑低值重复写入第二存储单元来替代实现相同的效果。 通过在刷新操作的测试期间将写入位线保持在逻辑低电平，可以增加通过第一存储器单元的写入晶体管的亚阈值漏电流。 这加速了第一个存储器值的放电，并确保在最坏情况下进行测试。

公开(公告)号：US5847990A

公开(公告)日：1998-12-08

申请号：US779993

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/41 ,  G11C11/56 ,  G11C11/00

CPC classification number: G11C11/5621 ,  G11C11/412 ,  G11C7/16

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract translation: 一种能够在存储单元中存储三种逻辑状态的存储电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由三态触发器的状态决定。 通过使电流被检测为正，负或零，可以用触发器的状态表示多于一个位的信息。

公开(公告)号：US5796650A

公开(公告)日：1998-08-18

申请号：US858270

申请日：1997-05-19

Applicant: Thomas R. Wik ,  Shahryar Aryani

Inventor： Thomas R. Wik ,  Shahryar Aryani

IPC: G11C11/405 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C11/4096

Abstract: A memory circuit wherein subthreshold leakage current may be reduced. The memory circuit includes a memory array composed of one or more storage cells that are each configured to store a memory value on a storage transistor. The storage cells further include a write transistor coupled to the storage transistor that is configured to allow data driven on a write bit line to be stored to the storage transistor. The write bit line is coupled to a write control unit, which includes a buffer and a offset voltage element. The buffer is configured to establish an output voltage on the write bit line in response to an input voltage. The offset voltage element is coupled to the buffer, and is configured to offset the output voltage on the write bit line by a predetermined amount. In one implementation of the write control unit, the buffer is formed by an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a diode-connected transistor coupled between the inverter and ground. The diode-connected transistor has the effect of holding the write bit line at a level equal to its threshold voltage when the n-channel transistor of the inverter is active. In another implementation, the buffer is also an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a pullup transistor that is active when the n-channel transitor of the inverter is active. The pullup transistor forms a voltage divider with the n-channel transistor, such that the voltage between the write bit line and ground is offset by an amount determined by the voltage drop across the pullup transistor. The offset voltage established by the write control unit biases the write transistor such that subthreshold leakage current may be reduced when the write transistor is off.

Abstract translation: 可以减小亚阈值泄漏电流的存储电路。 存储器电路包括由一个或多个存储单元组成的存储器阵列，每个存储单元被配置为将存储器值存储在存储晶体管上。 存储单元还包括耦合到存储晶体管的写入晶体管，其被配置为允许在写入位线上驱动的数据被存储到存储晶体管。 写位线耦合到写控制单元，写控制单元包括缓冲器和偏移电压元件。 缓冲器被配置为响应于输入电压在写位线上建立输出电压。 偏移电压元件耦合到缓冲器，并且被配置为将写入位线上的输出电压偏移预定量。 在写入控制单元的一个实现中，缓冲器由包括p沟道和n沟道晶体管的反相器形成。 偏置电压元件是连接在逆变器和地之间的二极管连接的晶体管。 二极管连接的晶体管具有在逆变器的n沟道晶体管处于活动状态时将写入位线保持在等于其阈值电压的电平的效果。 在另一实现中，缓冲器也是包括p沟道和n沟道晶体管的反相器。 偏移电压元件是一个上拉晶体管，当反相器的n沟道截止器有效时，它是有效的。 上拉晶体管与n沟道晶体管形成分压器，使得写位线和地之间的电压偏移由上拉晶体管两端的电压降决定的量。 由写入控制单元建立的偏移电压使写入晶体管偏置，使写入晶体管截止时亚阈值漏电流可能减小。

公开(公告)号：US5506519A

公开(公告)日：1996-04-09

申请号：US253795

申请日：1994-06-03

Applicant: Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

Inventor： Steven C. Avery ,  John S. Denker ,  Alexander G. Dickinson ,  Alan H. Kramer ,  Thomas R. Wik

IPC: H03K19/0948 ,  H03K3/356 ,  H03K19/00 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K19/0019 ,  H03K19/1738 ,  H03K3/356026 ,  H03K3/356121

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract translation: 无论逻辑信号输入到门的输出还是从门输出，节能逻辑门电路设计为时钟源提供基本恒定的负载。 门提供两个互补输出，并利用交叉耦合晶体管确保在逻辑输入无效后，输出保持有效（互补）。 两个块，每个具有耦合到时钟源并执行互补逻辑功能的节点，与用于对门的输出再充电的二极管相结合，将恒定负载呈现给时钟源。