公开(公告)号：US5903505A

公开(公告)日：1999-05-11

申请号：US858271

申请日：1997-05-19

Applicant: Thomas R. Wik ,  Tuan Phan ,  Thien Trieu

Inventor： Thomas R. Wik ,  Tuan Phan ,  Thien Trieu

IPC: G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/08 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/02 ,  G11C29/50

Abstract: A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value. Driving the write bit line low may be accomplished by repetitively reading the second memory cell. The same effect may alternately be achieved by repetitively writing a logic low value to the second memory cell. By keeping the write bit line at a logic low level during testing of refresh operations, the subthreshold leakage current through the write transistor of the first memory cell may be increased. This accelerates the discharge of the first memory value, and insures testing is performed near worst-case conditions.

Abstract translation: 一种用于测试存储器阵列的刷新操作的方法，其中可将亚阈值泄漏电流设置为接近最坏情况条件。 存储器阵列包括具有配置为存储第一存储器值的第一存储器单元的第一行存储器单元，以及具有被配置为存储第二存储器值的第二存储器单元的第二行存储器单元。 该方法包括将逻辑高值存储到第一存储器单元作为第一存储器值，随后将逻辑低值存储到第二存储器单元作为第二存储器值。 该方法还包括在等于与第一存储器单元相对应的刷新间隔的时间周期内重复驱动以逻辑低电平耦合到第一和第二存储器单元两者的写位线。 另外，该方法包括随后从第一存储器单元读取第一存储器值。 最后，如果第一存储器值仍然等于逻辑高值，则该方法包括指示第一存储器单元正在正常工作，或者如果第一存储器值等于逻辑低值，则指示第一存储器值发生故障。 将写位线驱动为低可以通过重复读取第二存储单元来实现。 可以通过将逻辑低值重复写入第二存储单元来替代实现相同的效果。 通过在刷新操作的测试期间将写入位线保持在逻辑低电平，可以增加通过第一存储器单元的写入晶体管的亚阈值漏电流。 这加速了第一个存储器值的放电，并确保在最坏情况下进行测试。