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公开(公告)号：US07028281B1
公开(公告)日：2006-04-11
申请号：US10194771
申请日：2002-07-12
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , G06F17/5054 , H01L2924/0002 , H03K19/17728 , H03K19/17784 , H01L2924/00
摘要： Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.
摘要翻译： 现场可编程门阵列（FPGA）可以根据本公开进行结构化以具有寄存器密集型架构，其针对逻辑块内的多个功能产生查找表（例如，4输入，基本LUT）中的每一个提供寄存器密集型结构， 多个块内可访问寄存器。 可以提供寄存器馈送多路复用器装置，用于允许多个寄存器中的每一个等效地捕获并存储由多个寄存器的相应的基本LUT输出的结果信号。 可以为每个基本LUT提供可登记的主和辅助馈通，使得LUT的本地采集的输入信号可以被馈送到相应的块内寄存器用于寄存器恢复目的，而不会完全消耗（浪费）查找资源 的相关的基本LUT。 可以进一步提供多级输入开关矩阵（ISM），用于从相邻的块互连线（AIL）和/或块内连接线（例如，FB）到基本LUT的采集和路由输入信号，并且 /或其各自的可注册馈通。 公开了利用许多块内寄存器和/或可注册馈通和/或多级ISM的技术来通过适当地配置这种寄存器密集型FPGA来有效地实现各种电路设计。
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2.发明授权Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility 有权具有CMOS驱动器门电流控制的输入缓冲器，可实现PCL，GTL或PECL的兼容性公开(公告)号：US06870391B1
公开(公告)日：2005-03-22
申请号：US10146769
申请日：2002-05-16
IPC分类号： G06F7/38 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/018585
摘要： An input/output buffer is provided which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a first pair of CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. Switching circuitry includes transistors which drive gates of the CMOS transistors to set the output (OUT) with a current level and a voltage level depending on a desired output drive current and voltage.
摘要翻译： 提供了一种输入/输出缓冲器，可用于使集成电路选择性地兼容多种接口类型之一，如PCI，GTL，PECL，ECL和SSTI。 输入缓冲器部分包括第一对CMOS晶体管，用于驱动类似于CMOS逻辑的VSS和VDD电压之间的输出（OUT）。 开关电路包括驱动CMOS晶体管的栅极的晶体管，以根据期望的输出驱动电流和电压将电流电平和电压电平设置为输出（OUT）。
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公开(公告)号：US06798244B1
公开(公告)日：2004-09-28
申请号：US10151753
申请日：2002-05-16
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K17/163
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The input buffer includes switching circuitry driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The switching circuitry includes components to prevent damage to low voltage transistors used in the output buffer should the output pad (PAD) voltage exceed VDD, or should charge buildup occur on the common well of PMOS transistors used in the output buffer exceed VDD.
摘要翻译： 输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。 输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。 输入缓冲器包括驱动多个CMOS缓冲晶体管的栅极的开关电路，以提供足够的电流用于快速开关，并且在切换之后限制电流以准备随后的输出转换。 如果输出缓冲器（PAD）电压超过VDD，或者在输出缓冲器中使用的PMOS晶体管的公共阱上的电荷积累超过VDD，则开关电路包括防止损坏输出缓冲器中使用的低压晶体管的组件。
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4.发明授权Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility 失效输出缓冲器，具有来自输入缓冲器的反馈，提供可选择的PCL，GTL或PECL兼容性公开(公告)号：US06657458B1
公开(公告)日：2003-12-02
申请号：US10146826
申请日：2002-05-16
IPC分类号： H03K19177
CPC分类号： H03K19/018585
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The signal from the PAD is further fed back through the input buffer portion which programmably set to operate in a PCI, PECL or GTL mode to control a node (INB). The node (INB) is used to control power switches driving the gates of CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. Pull-up and pull-down reference circuits provide references VRFPU, VRFPPU, VRFPD and VRFPPD to control the current of the output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.
摘要翻译： 输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。 输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。 来自PAD的信号通过可编程设置为以PCI，PECL或GTL模式操作以控制节点（INB）的输入缓冲器部分进一步反馈。 节点（INB）用于控制驱动CMOS缓冲晶体管的栅极的电源开关，以提供足够的电流用于快速开关，并在切换后限制电流以准备后续的输出转换。 上拉和下拉参考电路提供参考VRFPU，VRFPPU，VRFPD和VRFPPD，以在输出转换期间控制输出电流，同时在转换后以最小的电流水平将输出电压电平保持在所需电压。
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5.发明授权FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。
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6.发明授权Operational amplifier with CMOS transistors made using 2.5 volt process transistors 有权具有采用2.5伏过程晶体管的CMOS晶体管的运算放大器公开(公告)号：US06175266B1
公开(公告)日：2001-01-16
申请号：US09207558
申请日：1998-12-08
IPC分类号： G05F302
CPC分类号： G05F1/575
摘要： A power converter includes an opamp (FIG. 5) with CMOS transistors made using 2.5 volt process technology which tolerates a maximum gate voltage of 2.7 volts. The opamp is driven by a pin supply voltage (NV3EXT) with a maximum value of 3.6 volts. The connection of the transistors of the opamp (FIG. 5) provides a maximum gate to source, and gate to drain voltage on each transistor which is less than 2.7 volts when NV3EXT is at 3.6 volts. Further, the output (OUT) of the opamp (FIG. 5) is referenced to ground, rather than NV3EXT to prevent fluctuations in the input voltage offset relative to NV3EXT, and minimize variations in the output voltage margin of the power converter.
摘要翻译： 功率转换器包括具有使用2.5伏工艺技术制造的CMOS晶体管的运算放大器（图5），其允许2.7V的最大栅极电压。 运算放大器由最大值为3.6伏特的引脚电源电压（NV3EXT）驱动。 当NV3EXT为3.6伏时，运算放大器（图5）的晶体管的连接提供了每个晶体管上的最大栅极至源极以及小于2.7伏特的栅极至漏极电压。 此外，运算放大器（图5）的输出（OUT）参考地，而不是NV3EXT，以防止相对于NV3EXT的输入电压偏移的波动，并使功率转换器的输出电压余量的变化最小化。
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7.发明授权High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process 有权高压开关用于提供高于2.5伏特的电压，使用2.5伏工艺制造的晶体管公开(公告)号：US06169432A
公开(公告)日：2001-01-02
申请号：US09188778
申请日：1998-11-09
IPC分类号： H03B100
CPC分类号： H03K17/102
摘要： A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts. A PMOS transistor (366) has a gate tied to the drain of cascode (361) and provides Vcc to the switch output (n10). A PMOS transistor (368) has a gate tied to the gate of transistor 365 and supplies 4.5 volts to the switch output (n10). In operation, the switch (350) functions to selectively transition its output (n10) between Vcc and 4.5 volts without applying greater than 2.7 volts from the gate to source, gate to drain, or source to drain of any of its transistors.
摘要翻译： 提供由2.5伏过程晶体管组成的电压开关，其容许最大的栅极到源极，栅极到漏极或漏极到源极电压为2.7伏特。 电压开关晶体管被布置成在诸如2.5伏特的电压和诸如4.5伏特的高得多的电压之间切换。 在一个实施例（350）中，电压开关包括提供给NMOS共源共栅连接晶体管（360）的源极的输入端。 反相器（354）将NMOS共源共栅（360）的源极连接到另一个NMOS共源共栅（361）的源极。 共源共栅晶体管被定义为连接，使得其通过在栅极电压固定的情况下改变源极电压来导通和关断，而不是改变栅极电压。 级联（360,361）的栅极连接到Vcc（2.5伏特）。 PMOS级联晶体管（362）和（363）将各自的共源共栅晶体管（360）和（361）的漏极连接到PMOS晶体管（364）和（365）。 PMOS晶体管（364）和（365）具有连接到4.5伏特的源极。 PMOS晶体管（366）具有连接到共源共栅（361）的漏极的栅极，并向开关输出（n10）提供Vcc。 PMOS晶体管（368）具有连接到晶体管365的栅极的栅极，并向开关输出（n10）提供4.5伏特。 在操作中，开关（350）用于选择性地将其输出（n10）在Vcc和4.5V之间转变，而不施加大于2.7伏的栅极至源极，栅极至漏极或其任何晶体管的源极到漏极。
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8.发明授权High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device 失效高压检测器用于控制2.5伏半导体工艺装置的电源电压泵
公开(公告)号：US6163175A
公开(公告)日：2000-12-19
申请号：US276990
申请日：1999-03-26
CPC分类号： H03K5/2481 , H02M3/073
摘要： A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.
摘要翻译： 高电压检测器电路（图2）通过在基准线电压（V2）下降到参考电压以下时，用信号（PUMPON）转动电荷泵来维持由电荷泵驱动的参考线上的电压（V2） （V1）加上CMOS晶体管阈值电压。 高电压检测器还被配置为使用具有最大栅极漏极或栅极至源极电压的晶体管，栅极至源极电压超过芯片的引脚电源电压。 高电压检测器包括由弱电流源驱动的一系列电流镜构成的比较器，使得电路能够使用最小量的功率。
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9.发明授权Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。 每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。
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10.发明授权Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan 有权多端口SRAM单元阵列具有多个写入路径，包括用于通过可寻址端口进行写入和通过串行边界扫描
公开(公告)号：US6097664A
公开(公告)日：2000-08-01
申请号：US235356
申请日：1999-01-21
CPC分类号： G11C8/16
摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.
摘要翻译： 串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。 响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。
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