公开(公告)号：US20240077534A1

公开(公告)日：2024-03-07

申请号：US18150830

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US12066489B2

公开(公告)日：2024-08-20

申请号：US18150830

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318541 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US20240361383A1

公开(公告)日：2024-10-31

申请号：US18770809

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318541 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.