A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.