公开(公告)号：US12216981B2

公开(公告)日：2025-02-04

申请号：US18448143

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US12009260B2

公开(公告)日：2024-06-11

申请号：US17011801

申请日：2020-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ka Fai Chang ,  Fong-Yuan Chang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L21/822 ,  G06F30/398 ,  G06F119/06 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/8221 ,  G06F30/398 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/42 ,  G06F2119/06

Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

公开(公告)号：US11715668B2

公开(公告)日：2023-08-01

申请号：US17371438

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jr Huang ,  William Wu Shen ,  Chin-Her Chien ,  Chin-Chou Liu ,  Yun-Han Lee

IPC: H01Q1/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/48 ,  H01Q9/0407 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2924/1423 ,  H01L2924/157 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/131 ,  H01L2924/014

Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.

公开(公告)号：US09659133B2

公开(公告)日：2017-05-23

申请号：US14056420

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Hung Lin ,  Chi Wei Hu ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Chin-Chou Liu

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.

公开(公告)号：US20240379746A1

公开(公告)日：2024-11-14

申请号：US18784083

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method of forming a semiconductor structure including a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

公开(公告)号：US12062641B2

公开(公告)日：2024-08-13

申请号：US18322467

申请日：2023-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Lin Chen ,  Hui-Yu Lee ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Chin-Chou Liu

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/08145 ,  H01L2224/83896 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2924/1206 ,  H01L2924/19042

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

公开(公告)号：US12039244B2

公开(公告)日：2024-07-16

申请号：US17752474

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: G06F30/392 ,  G06F30/27 ,  G06F115/02 ,  G06F115/12 ,  G06F119/18

CPC classification number: G06F30/392 ,  G06F30/27 ,  G06F2115/02 ,  G06F2115/12 ,  G06F2119/18

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.

公开(公告)号：US11923271B2

公开(公告)日：2024-03-05

申请号：US17380305

申请日：2021-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Noor E. V. Mohamed ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Chin-Chou Liu

IPC: H01L23/48 ,  H01L21/822 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/8221 ,  H01L24/17 ,  H01L25/0657

Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

公开(公告)号：US11532580B2

公开(公告)日：2022-12-20

申请号：US16883929

申请日：2020-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chou Tsai ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.

公开(公告)号：US11387177B2

公开(公告)日：2022-07-12

申请号：US16442955

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Her Chien ,  Po-Hsiang Huang ,  Cheng-Hung Yeh ,  Tai-Yu Wang ,  Ming-Ke Tsai ,  Yao-Hsien Tsai ,  Kai-Yun Lin ,  Chin-Yuan Huang ,  Kai-Ming Liu ,  Fong-Yuan Chang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.