- Patent Title: Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same
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Application No.: US18322467Application Date: 2023-05-23
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Publication No.: US12062641B2Publication Date: 2024-08-13
- Inventor: Chih-Lin Chen , Hui-Yu Lee , Fong-Yuan Chang , Po-Hsiang Huang , Chin-Chou Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/48 ; H01L21/768 ; H01L23/00 ; H01L23/48 ; H01L23/522 ; H01L23/528 ; H01L23/538 ; H01L25/00 ; H01L49/02

Abstract:
An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.
Public/Granted literature
- US20230299052A1 INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME Public/Granted day:2023-09-21
Information query
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