公开(公告)号：US20230052136A1

公开(公告)日：2023-02-16

申请号：US17834289

申请日：2022-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10

Abstract: An integrated circuit (IC) device includes a chip having a semiconductor substrate and a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

公开(公告)号：US20230041839A1

公开(公告)日：2023-02-09

申请号：US17752474

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: G06F30/392 ,  G06F30/27

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.

公开(公告)号：US20240379746A1

公开(公告)日：2024-11-14

申请号：US18784083

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method of forming a semiconductor structure including a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

公开(公告)号：US12039244B2

公开(公告)日：2024-07-16

申请号：US17752474

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang ,  Jheng-Hong Jiang ,  Chin-Chou Liu ,  Long Song Lin

IPC: G06F30/392 ,  G06F30/27 ,  G06F115/02 ,  G06F115/12 ,  G06F119/18

CPC classification number: G06F30/392 ,  G06F30/27 ,  G06F2115/02 ,  G06F2115/12 ,  G06F2119/18

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.