公开(公告)号：US11387177B2

公开(公告)日：2022-07-12

申请号：US16442955

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Her Chien ,  Po-Hsiang Huang ,  Cheng-Hung Yeh ,  Tai-Yu Wang ,  Ming-Ke Tsai ,  Yao-Hsien Tsai ,  Kai-Yun Lin ,  Chin-Yuan Huang ,  Kai-Ming Liu ,  Fong-Yuan Chang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

公开(公告)号：US11367695B2

公开(公告)日：2022-06-21

申请号：US16439295

申请日：2019-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan Chang ,  Cheng-Hung Yeh ,  Hsiang-Ho Chang ,  Po-Hsiang Huang ,  Chin-Her Chien ,  Sheng-Hsiung Chen ,  Aftab Alam Khan ,  Keh-Jeng Chang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  G06F30/36 ,  G06F111/20 ,  G06F119/06

Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.

公开(公告)号：US20240386183A1

公开(公告)日：2024-11-21

申请号：US18785924

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheng-Hung Yeh ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Yi-Kan Cheng ,  Hsiu-Chuan Shu

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.