公开(公告)号：US20220320018A1

公开(公告)日：2022-10-06

申请号：US17843746

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Cheng-Hung YEH ,  Hsiang-Ho CHANG ,  Po-Hsiang HUANG ,  Chin-Her CHIEN ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN ,  Keh-Jeng CHANG ,  Chin-Chou LIU ,  Yi-Kan CHENG

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  G06F30/36

Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.

公开(公告)号：US20220149020A1

公开(公告)日：2022-05-12

申请号：US17367867

申请日：2021-07-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Lee-Chung Lu ,  Jyh Chwen Frank Lee ,  Po-Hsiang Huang ,  Xinyu Bao ,  Sam Vaziri

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/373 ,  H01L21/48

Abstract: A package structure includes a solder feature, a first redistribution layer structure on the solder feature, and a die mounted on and electrically coupled to the first redistribution layer structure. The first redistribution layer structure includes one or more dielectric layers filled with a heat conductive dielectric material.

公开(公告)号：US20200043873A1

公开(公告)日：2020-02-06

申请号：US16439295

申请日：2019-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Cheng-Hung YEH ,  Hsiang-Ho CHANG ,  Po-Hsiang HUANG ,  Chin-Her CHIEN ,  Sheng-Hsiung CHEN ,  Aftab Alam KHAN ,  Keh-Jeng CHANG ,  Chin-Chou LIU ,  Yi-Kan CHENG

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  G06F17/50

Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.

公开(公告)号：US20240386183A1

公开(公告)日：2024-11-21

申请号：US18785924

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheng-Hung Yeh ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Yi-Kan Cheng ,  Hsiu-Chuan Shu

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20240354487A1

公开(公告)日：2024-10-24

申请号：US18762219

申请日：2024-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fong-yuan CHANG ,  Chun-Chen CHEN ,  Sheng-Hsiung CHEN ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Jung-Chan YANG ,  Lee-Chung LU ,  Po-Hsiang HUANG

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20240413052A1

公开(公告)日：2024-12-12

申请号：US18790042

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hsiang HUANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Fong-yuan CHANG ,  Hui Yu LEE

IPC: H01L23/42 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US20220359392A1

公开(公告)日：2022-11-10

申请号：US17389141

申请日：2021-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fei Fan DUAN ,  Fong-yuan CHANG ,  Chi-Yu LU ,  Po-Hsiang HUANG ,  Chih-Liang CHEN

IPC: H01L23/528 ,  H01L23/522 ,  G06F30/398

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.

公开(公告)号：US20240096800A1

公开(公告)日：2024-03-21

申请号：US18519513

申请日：2023-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fei Fan DUAN ,  Fong-yuan CHANG ,  Chi-Yu LU ,  Po-Hsiang HUANG ,  Chih-Liang CHEN

IPC: H01L23/528 ,  G06F30/398 ,  H01L23/522

CPC classification number: H01L23/5283 ,  G06F30/398 ,  H01L23/5226 ,  G06F2119/12

Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.