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    LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS
    2.
    发明公开
    LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS 审中-公开

    公开(公告)号：US20230376661A1

    公开(公告)日：2023-11-23

    申请号：US18362938

    申请日：2023-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Lin LIU ,  Jerry Chang-Jui KAO ,  Wei-Hsiang MA ,  Lee-Chung LU ,  Fong-Yuan CHANG ,  Sheng-Hsiung CHEN ,  Shang-Chih HSIEH

    IPC: G06F30/327

    CPC classification number: G06F30/327 ,  G06F2111/06

    Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

    SEMICONDUCTOR DEVICE WITH CELL REGION, METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH CELL REGION, METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME 有权

    公开(公告)号：US20210209287A1

    公开(公告)日：2021-07-08

    申请号：US17212775

    申请日：2021-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Sheng-Hsiung CHEN ,  Fong-Yuan CHANG ,  Ho Che YU

    IPC: G06F30/398 ,  G06F30/392 ,  H01L27/11575

    Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

    SEMICONDUCTOR DEVICE WITH CELL REGION
    6.
    发明公开
    SEMICONDUCTOR DEVICE WITH CELL REGION 审中-公开

    公开(公告)号：US20230177249A1

    公开(公告)日：2023-06-08

    申请号：US18161657

    申请日：2023-01-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Sheng-Hsiung CHEN ,  Fong-Yuan CHANG ,  Ho Che YU

    IPC: G06F30/398 ,  G06F30/392 ,  H10B43/50

    CPC classification number: G06F30/398 ,  G06F30/392 ,  H10B43/50

    Abstract: A semiconductor device includes: first fins (F-fins) and second fins (S-fin) arranged in a first row having a single-row height and that includes an alpha cell region and a beta cell region. The alpha cell region includes a first F-fin, a first S-fin and a first gate structure overlapping each of the first F-fin and the first S-fin. The first gate structure does not overlap top and bottom edges of the alpha cell region. The beta cell region includes second and third F-fins, second and third S-fins and a second gate structure overlapping each of the second F-fin and second S-fin and at least one of the third F-fin or the third S-fin. A top edge of the beta cell region being co-track aligned with the third F-fin. A bottom edge of the beta cell region being co-track aligned with the third S-fin.

    METHOD AND SYSTEM OF EXPANDING SET OF STANDARD CELLS WHICH COMPRISE A LIBRARY
    10.
    发明申请
    METHOD AND SYSTEM OF EXPANDING SET OF STANDARD CELLS WHICH COMPRISE A LIBRARY 审中-公开

    公开(公告)号：US20200272778A1

    公开(公告)日：2020-08-27

    申请号：US15930010

    申请日：2020-05-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Lin LIU ,  Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Lee-Chung LU ,  Shang-Chih HSIEH ,  Wei-Hsiang MA

    IPC: G06F30/327

    Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram, selecting one of the recurrent ad hoc groups (selected group) such that: the elementary standard cells in the selected group have connections representing a corresponding logic circuit; each elementary standard cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of the corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.

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