Invention Application
- Patent Title: METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING PROTRUDING PIN CELL REGIONS AND SEMICONDUCTOR DEVICE BASED ON SAME
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Application No.: US17131038Application Date: 2020-12-22
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Publication No.: US20210110097A1Publication Date: 2021-04-15
- Inventor: Fong-Yuan CHANG , Chin-Chou LIU , Sheng-Hsiung CHEN , Po-Hsiang HUANG
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F30/394 ; G06F30/392 ; G03F1/70

Abstract:
A method (of generating a layout diagram) includes: generating a shell including wiring patterns in a first layer of metallization, the wiring patterns having long axes which are substantially aligned with corresponding tracks that extend in a first direction, the wiring patterns having a default arrangement which has, relative to the corresponding tracks, a first amount of free space; and refining the shell into a cell, the refining including selectively shrinking, in the first direction, one or more of the wiring patterns resulting in a second amount of free space, the second amount being greater than the first amount, increasing, in the first direction, one or more chosen ones of the wiring patterns (chosen patterns), and backfilling the second amount of free space with one or more of at least one dummy pattern or at least one wiring pattern.
Information query