公开(公告)号：US12068305B2

公开(公告)日：2024-08-20

申请号：US17216420

申请日：2021-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: H01L21/70 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F30/39 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/7851

Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.

公开(公告)号：US20220352072A1

公开(公告)日：2022-11-03

申请号：US17866880

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

公开(公告)号：US10964684B2

公开(公告)日：2021-03-30

申请号：US16405898

申请日：2019-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: H01L21/336 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  G06F30/39

Abstract: A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.

公开(公告)号：US11409937B2

公开(公告)日：2022-08-09

申请号：US17131128

申请日：2020-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/398

Abstract: A method of manufacturing a semiconductor device that includes identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights. The method also includes replacing cells in the first row which have the H1 height with corresponding substitute cells, each substitute cell being correspondingly taller relative to the second direction and correspondingly narrower relative to the first direction, the replacing thereby increasing a density of the second row at least without substantially increasing a density of the first row.

公开(公告)号：US12211793B2

公开(公告)日：2025-01-28

申请号：US17866880

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/535 ,  H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L27/118

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

公开(公告)号：US10262981B2

公开(公告)日：2019-04-16

申请号：US15465167

申请日：2017-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Po-Hsiang Huang ,  Lipen Yuan

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.

公开(公告)号：US12086524B2

公开(公告)日：2024-09-10

申请号：US18362957

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207

Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.

公开(公告)号：US11935825B2

公开(公告)日：2024-03-19

申请号：US16554035

申请日：2019-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou Sio ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Lipen Yuan

IPC: H01L23/522 ,  G06F30/394 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L23/5221 ,  G06F30/394 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0924

Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

公开(公告)号：US11797746B2

公开(公告)日：2023-10-24

申请号：US17865272

申请日：2022-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207

Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.

公开(公告)号：US10797041B2

公开(公告)日：2020-10-06

申请号：US16205014

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Po-Hsiang Huang ,  Lipen Yuan

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.