公开(公告)号：US10970450B2

公开(公告)日：2021-04-06

申请号：US15782232

申请日：2017-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Ho Che Yu ,  Lee-Chung Lu ,  Ni-Wan Fan ,  Po-Hsiang Huang ,  Chi-Yu Lu ,  Jeo-Yen Lee

IPC: G06F30/392 ,  H01L27/118 ,  G06F30/398 ,  G06F30/39 ,  H01L23/538 ,  H01L27/02

Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.

公开(公告)号：US12211793B2

公开(公告)日：2025-01-28

申请号：US17866880

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/535 ,  H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L27/118

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

公开(公告)号：US20220352072A1

公开(公告)日：2022-11-03

申请号：US17866880

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

公开(公告)号：US11281836B2

公开(公告)日：2022-03-22

申请号：US17222021

申请日：2021-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Ho Che Yu ,  Lee-Chung Lu ,  Ni-Wan Fan ,  Po-Hsiang Huang ,  Chi-Yu Lu ,  Jeo-Yen Lee

IPC: G06F30/392 ,  H01L27/118 ,  G06F30/398 ,  G06F30/39 ,  H01L23/538 ,  H01L27/02

Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.