公开(公告)号：US20190013268A1

公开(公告)日：2019-01-10

申请号：US16127645

申请日：2018-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/49 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US09698101B2

公开(公告)日：2017-07-04

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20170012107A1

公开(公告)日：2017-01-12

申请号：US14795984

申请日：2015-07-10

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： Chanro Park ,  Injo Ok

IPC: H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract translation: 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

公开(公告)号：US09583584B2

公开(公告)日：2017-02-28

申请号：US14795984

申请日：2015-07-10

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： Chanro Park ,  Injo Ok

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L21/82

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract translation: 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

公开(公告)号：US20170062325A1

公开(公告)日：2017-03-02

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

Abstract translation: 自对准互连结构包括在衬底中图案化的翅片结构; 设置在所述鳍结构上的外延触点; 第一金属栅极和第二金属栅极，其设置在外延接触面上并基本上垂直于外延接触，第一金属栅极和第二金属栅极基本上彼此平行; 以及在第一和第二金属栅极之间的区域中与基板接触并与之接触的金属接触。

公开(公告)号：US10325848B2

公开(公告)日：2019-06-18

申请号：US16127645

申请日：2018-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L29/49 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US10236253B2

公开(公告)日：2019-03-19

申请号：US15484309

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/417

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20170221808A1

公开(公告)日：2017-08-03

申请号：US15484309

申请日：2017-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V.V.S. Surisetty ,  Ruilong Xie

IPC: H01L23/528 ,  H01L21/306 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US12144271B2

公开(公告)日：2024-11-12

申请号：US17444841

申请日：2021-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg Gluschenkov ,  Alexander Reznicek ,  Youngseok Kim ,  Injo Ok ,  Soon-Cheon Seo

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

公开(公告)号：US20240237544A1

公开(公告)日：2024-07-11

申请号：US18150816

申请日：2023-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin W. Brew ,  Ching-Tzu Chen ,  Timothy Mathew Philip ,  JIN PING HAN ,  Injo Ok

IPC: H10N50/10 ,  H01L23/528 ,  H10N50/01

CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10N50/01

Abstract: Embodiments of present invention provide a vertical magnetic tunnel junction (MTJ) structure. The structure includes an L-shaped MTJ stack including an L-shaped reference layer conformally on an L-shaped performance enhancing layer; an L-shaped tunnel barrier layer conformally on the L-shaped reference layer; and an L-shaped free layer conformally on the L-shaped tunnel barrier layer, where a vertical portion of the L-shaped MTJ stack is adjacent to a sidewall of a metal stud, the metal stud being directly on top of a metal wire in a dielectric layer. The structure further includes a first and a second electrode contacting a horizontal portion and a vertical portion of the L-shaped MTJ stack. A method of forming the same is also provided.