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    VERTICAL MAGNETIC TUNNEL JUNCTION DEVICE
    1.
    发明公开
    VERTICAL MAGNETIC TUNNEL JUNCTION DEVICE 审中-公开

    公开(公告)号：US20240237544A1

    公开(公告)日：2024-07-11

    申请号：US18150816

    申请日：2023-01-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kevin W. Brew ,  Ching-Tzu Chen ,  Timothy Mathew Philip ,  JIN PING HAN ,  Injo Ok

    IPC: H10N50/10 ,  H01L23/528 ,  H10N50/01

    CPC classification number: H10N50/10 ,  H01L23/5283 ,  H10N50/01

    Abstract: Embodiments of present invention provide a vertical magnetic tunnel junction (MTJ) structure. The structure includes an L-shaped MTJ stack including an L-shaped reference layer conformally on an L-shaped performance enhancing layer; an L-shaped tunnel barrier layer conformally on the L-shaped reference layer; and an L-shaped free layer conformally on the L-shaped tunnel barrier layer, where a vertical portion of the L-shaped MTJ stack is adjacent to a sidewall of a metal stud, the metal stud being directly on top of a metal wire in a dielectric layer. The structure further includes a first and a second electrode contacting a horizontal portion and a vertical portion of the L-shaped MTJ stack. A method of forming the same is also provided.

    PHASE CHANGE MEMORY CELL WITH DOUBLE ACTIVE VOLUME
    3.
    发明公开
    PHASE CHANGE MEMORY CELL WITH DOUBLE ACTIVE VOLUME 审中-公开

    公开(公告)号：US20230284541A1

    公开(公告)日：2023-09-07

    申请号：US17653143

    申请日：2022-03-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Timothy Mathew Philip ,  JIN PING HAN ,  Kevin W. Brew ,  Ching-Tzu Chen ,  Injo Ok

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/06 ,  H01L45/1293 ,  H01L45/1233 ,  H01L45/1608 ,  G11C13/004 ,  G11C13/0004 ,  G11C2013/0045

    Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

    MEDIA CAPTURE DEVICE WITH POWER SAVING AND ENCRYPTION FEATURES FOR PARTITIONED NEURAL NETWORK
    5.
    发明申请
    MEDIA CAPTURE DEVICE WITH POWER SAVING AND ENCRYPTION FEATURES FOR PARTITIONED NEURAL NETWORK 有权

    公开(公告)号：US20220156550A1

    公开(公告)日：2022-05-19

    申请号：US16952314

    申请日：2020-11-19

    Applicant: International Business Machines Corporation

    Inventor： Xin Zhang ,  Xiaodong Cui ,  JIN PING HAN

    IPC: G06N3/04 ,  G06F21/62 ,  G06F1/3287 ,  G06F1/3246

    Abstract: A method for power saving and encryption during analysis of media captured by an information capture device using a partitioned neural network includes replicating, by an information capture device, an artificial neural network (ANN) from a computer server to the information capture device. The ANN on the computer server and a replicated ANN, both, include M layers. The method further includes, in response to captured data being input to be processed, partially processing, by the information capture device, the captured data by executing a first k layers using the replicated ANN, wherein only the k layers are selected to execute on the information capture device. The method further includes transmitting, by the information capture device, an output of the k-th layer to the computer server, which partially processes the captured data by executing the remainder of the M layers using the ANN and the output of the k-th layer.

    PHASE CHANGE MULTILAYER HETEROSTRUCTURE WITH MULTIPLE HEATERS
    7.
    发明公开
    PHASE CHANGE MULTILAYER HETEROSTRUCTURE WITH MULTIPLE HEATERS 审中-公开

    公开(公告)号：US20240081159A1

    公开(公告)日：2024-03-07

    申请号：US17929330

    申请日：2022-09-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ching-Tzu Chen ,  Kevin W. Brew ,  JIN PING HAN ,  Timothy Mathew Philip ,  Injo Ok

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1608 ,  H01L45/1666

    Abstract: A structure including alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A structure including horizontally aligned alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A method including forming alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode.

    MULTI-TERMINAL CROSS-POINT SYNAPTIC DEVICE USING NANOCRYSTAL DOT STRUCTURES
    8.
    发明申请
    MULTI-TERMINAL CROSS-POINT SYNAPTIC DEVICE USING NANOCRYSTAL DOT STRUCTURES 审中-公开

    公开(公告)号：US20200005129A1

    公开(公告)日：2020-01-02

    申请号：US16021824

    申请日：2018-06-28

    Applicant: International Business Machines Corporation

    Inventor： Kevin K. Chan ,  Martin M. Frank ,  JIN PING HAN

    IPC: G06N3/063 ,  G06N3/08

    Abstract: Described herein is a crossbar array that includes a cross-point synaptic device at each of a plurality of crosspoints. The cross-point synaptic device includes a weight storage element comprising a set of nanocrystal dots. Further, the cross-point synaptic device includes at least three terminals for interacting with the weight storage element, wherein a weight is stored in the weight storage element by sending a first electric pulse via a gate terminal from the at least three terminals, the first electric pulse causes the nanocrystal dots to store a corresponding charge, and the weight is erased from the weight storage element by sending a second electric pulse via the gate terminal, the second electric pulse having an opposite polarity of the first electric pulse.

    ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION
    9.
    发明公开
    ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION 审中-公开

    公开(公告)号：US20240103065A1

    公开(公告)日：2024-03-28

    申请号：US17954107

    申请日：2022-09-27

    Applicant: International Business Machines Corporation

    Inventor： Arvind Kumar ,  Ramachandra Divakaruni ,  Mukta Ghate Farooq ,  John W. Golz ,  JIN PING HAN ,  Mounir Meghelli

    IPC: G01R31/28 ,  G01R31/3187 ,  G06F13/40

    CPC classification number: G01R31/2843 ,  G01R31/3187 ,  G06F13/4027 ,  G06F13/4068

    Abstract: A semiconductor integrated circuit device includes: an active bridge; a first chiplet and a second chiplet mounted onto the active bridge; and a short-to-long converter circuit (SLCC) that has analog and digital portions. The active bridge includes at least the analog portion of the SLCC, which is electrically connected to at least the first chiplet; and a short-reach physical layer that electrically connects the first chiplet and the second chiplet. The first chiplet includes a first logic core; a first chiplet interface that is electrically connected between the first logic core and the SLCC; and a second chiplet interface that is electrically connected between the first logic core and the second chiplet. The second chiplet includes a second logic core; and a third chiplet interface that is electrically connected between the second logic core and the second chiplet interface. The active bridge also can include a built-in-self-test (BIST) circuit.

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