公开(公告)号：US11233148B2

公开(公告)日：2022-01-25

申请号：US16649304

申请日：2017-11-06

申请人： INTEL CORPORATION

发明人： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

摘要： Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US10985263B2

公开(公告)日：2021-04-20

申请号：US16465763

申请日：2016-12-31

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Van H. Le ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

摘要： An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US10886408B2

公开(公告)日：2021-01-05

申请号：US16327206

申请日：2016-09-29

申请人： INTEL CORPORATION

发明人： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/20 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/26 ,  H01L21/8252 ,  H01L29/16

摘要： Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

公开(公告)号：US20200266296A1

公开(公告)日：2020-08-20

申请号：US16649304

申请日：2017-11-06

申请人： INTEL CORPORATION

发明人： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

摘要： Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US10153372B2

公开(公告)日：2018-12-11

申请号：US15117590

申请日：2014-03-27

申请人： INTEL CORPORATION

发明人： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Willy Rachmady ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20180248028A1

公开(公告)日：2018-08-30

申请号：US15755489

申请日：2015-09-25

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Matthew V. Metz ,  Harold W. Kennel ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L27/092

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778

摘要： III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

公开(公告)号：US09698265B2

公开(公告)日：2017-07-04

申请号：US15045666

申请日：2016-02-17

申请人： Intel Corporation

发明人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/20 ,  H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

摘要： Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

公开(公告)号：US09570614B2

公开(公告)日：2017-02-14

申请号：US14914102

申请日：2013-09-27

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niti Goel ,  Van H. Le ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Stephen M. Cea ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/267

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

摘要翻译： 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US11764275B2

公开(公告)日：2023-09-19

申请号：US16074373

申请日：2016-04-01

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Glenn A. Glass ,  Harold W. Kennel ,  Anand S. Murthy ,  Willy Rachmady ,  Gilbert Dewey ,  Sean T. Ma ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/417 ,  H01L29/201 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20220059656A1

公开(公告)日：2022-02-24

申请号：US17453088

申请日：2021-11-01

申请人： Intel Corporation

发明人： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.