公开(公告)号：US20210074823A1

公开(公告)日：2021-03-11

申请号：US17082726

申请日：2020-10-28

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Karthik Jambunathan ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Patrick Morrow ,  Mauro J. Kobrinsky

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

摘要： Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

公开(公告)号：US10748900B2

公开(公告)日：2020-08-18

申请号：US15771080

申请日：2015-12-22

申请人： Intel Corporation

发明人： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/088

摘要： Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.

公开(公告)号：US10559683B2

公开(公告)日：2020-02-11

申请号：US15504171

申请日：2014-09-19

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/201 ,  H01L29/423

摘要： Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

公开(公告)号：US10461193B2

公开(公告)日：2019-10-29

申请号：US15575322

申请日：2015-05-27

申请人： Intel Corporation

发明人： Chandra S. Mohapatra ,  Gilbert Dewey ,  Anand S. Murthy ,  Glenn A. Glass ,  Willy Rachmady ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz

IPC分类号： H01L29/00 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

摘要： Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

公开(公告)号：US10340374B2

公开(公告)日：2019-07-02

申请号：US15755450

申请日：2015-09-25

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/201 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06

摘要： Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US20170229543A1

公开(公告)日：2017-08-10

申请号：US15504280

申请日：2014-09-19

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/10 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

公开(公告)号：US11276755B2

公开(公告)日：2022-03-15

申请号：US16303654

申请日：2016-06-17

申请人： Intel Corporation

发明人： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

摘要： Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US10886408B2

公开(公告)日：2021-01-05

申请号：US16327206

申请日：2016-09-29

申请人： INTEL CORPORATION

发明人： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/20 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/26 ,  H01L21/8252 ,  H01L29/16

摘要： Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

公开(公告)号：US10559689B2

公开(公告)日：2020-02-11

申请号：US15777707

申请日：2015-12-24

申请人： INTEL CORPORATION

发明人： Karthik Jambunathan ,  Glenn A. Glass ,  Anand S. Murthy ,  Jacob M. Jensen ,  Daniel B. Aubertine ,  Chandra S. Mohapatra

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/786

摘要： Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

公开(公告)号：US10483353B2

公开(公告)日：2019-11-19

申请号：US15778863

申请日：2015-12-24

申请人： INTEL CORPORATION

发明人： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/092 ,  H01L29/786

摘要： Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).