公开(公告)号：US12170273B2

公开(公告)日：2024-12-17

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US12100705B2

公开(公告)日：2024-09-24

申请号：US17825664

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Yih Wang ,  Rishabh Mehandru ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Mark Bohr ,  Marni Nabors

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76877 ,  H01L21/823431 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US20230420528A1

公开(公告)日：2023-12-28

申请号：US17851658

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Patrick Morrow ,  Marko Radosavljevic ,  Jami A. Wiedemer ,  Subrina Rafique ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/0847 ,  H01L29/401 ,  H01L27/088 ,  H01L29/0673

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

公开(公告)号：US11817442B2

公开(公告)日：2023-11-14

申请号：US17114700

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L25/18 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US11616015B2

公开(公告)日：2023-03-28

申请号：US17127863

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US11367796B2

公开(公告)日：2022-06-21

申请号：US16134817

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Mauro J. Kobrinsky ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

公开(公告)号：US11257822B2

公开(公告)日：2022-02-22

申请号：US16691163

申请日：2019-11-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC: H01L27/108 ,  H01L29/78 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US11139241B2

公开(公告)日：2021-10-05

申请号：US16348105

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L27/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US20210111115A1

公开(公告)日：2021-04-15

申请号：US17127863

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC: H01L23/528 ,  H01L29/78 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  G06F30/392

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.