公开(公告)号：US12014996B2

公开(公告)日：2024-06-18

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US20210407932A1

公开(公告)日：2021-12-30

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/762

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US11690211B2

公开(公告)日：2023-06-27

申请号：US17511646

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66 ,  H10B10/00

CPC classification number: H10B12/30 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/32 ,  H01L24/83 ,  H01L28/60 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78681 ,  H10B12/05 ,  H10B12/50 ,  H01L2224/32225 ,  H01L2924/1436 ,  H01L2924/1437 ,  H10B10/12

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20210125990A1

公开(公告)日：2021-04-29

申请号：US16667740

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20240222447A1

公开(公告)日：2024-07-04

申请号：US18090048

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Reken Patel ,  Conor P. Puls ,  Krishna Ganesan ,  Akitomo Matsubayashi ,  Diana Ivonne Paredes ,  Sunzida Ferdous ,  Brian Greene ,  Lateef Uddin Syed ,  Kyle T. Horak ,  Lin Hu ,  Anupama Bowonder ,  Swapnadip Ghosh ,  Amritesh Rai ,  Shruti Subramanian ,  Gordon S. Freeman

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.

公开(公告)号：US11239238B2

公开(公告)日：2022-02-01

申请号：US16667740

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20250006579A1

公开(公告)日：2025-01-02

申请号：US18216476

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Avijit Barik ,  Tao Chu ,  Minwoo Jang ,  Aurelia Wang ,  Conor P. Puls

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

Abstract: Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

公开(公告)号：US20240145410A1

公开(公告)日：2024-05-02

申请号：US18404708

申请日：2024-01-04

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.