公开(公告)号：US20220028779A1

公开(公告)日：2022-01-27

申请号：US17493715

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11996362B2

公开(公告)日：2024-05-28

申请号：US17493715

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/30604 ,  H01L21/768 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/785 ,  H01L29/7851

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11682664B2

公开(公告)日：2023-06-20

申请号：US16263093

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Srinivasa Chaitanya Gadigatla ,  Ranjith Kumar ,  Marni Nabors ,  Quan Phan

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  G06F30/394

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11803 ,  G06F30/394

Abstract: An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.

公开(公告)号：US12067338B2

公开(公告)日：2024-08-20

申请号：US17585101

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L27/00 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US11409935B2

公开(公告)日：2022-08-09

申请号：US16649800

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Srinivasa Chaitanya Gadigatla ,  Tamanna Husain ,  Abhinand Ramakrishnan ,  James Graeber ,  Kohinoor Basu

IPC: G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  H01L27/02 ,  G06F111/20 ,  G06F119/12

Abstract: An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.

公开(公告)号：US20190312023A1

公开(公告)日：2019-10-10

申请号：US16348105

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/768

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11764219B2

公开(公告)日：2023-09-19

申请号：US16700064

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Harshitha Vishwanath ,  Renukprasad Hiremath ,  Sukru Yemenicioglu ,  Ranjith Kumar ,  Ruth Amy Brain

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.

公开(公告)号：US11522072B2

公开(公告)日：2022-12-06

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/45 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US11139241B2

公开(公告)日：2021-10-05

申请号：US16348105

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L27/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11068640B2

公开(公告)日：2021-07-20

申请号：US16649588

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Mark T. Bohr ,  Ruth A. Brain ,  Marni Nabors ,  Tai-Hsuan Wu ,  Sourav Chakravarty

IPC: G06F30/3953 ,  G06F113/18 ,  G06F115/08 ,  H01L23/50 ,  H01L23/522

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.