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    Replacement metal COB integration process for embedded DRAM
    1.
    发明授权
    Replacement metal COB integration process for embedded DRAM 有权

    公开(公告)号：US11723188B2

    公开(公告)日：2023-08-08

    申请号：US16024578

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Uygar Avci ,  Ian Young ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain

    IPC: H01L23/522 ,  H01L21/768 ,  H10B12/00 ,  H01L49/02

    CPC classification number: H10B12/315 ,  H01L21/76808 ,  H01L21/76843 ,  H01L23/5226 ,  H01L28/91 ,  H10B12/033 ,  H10B12/50

    Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSTOR GATE
    5.
    发明申请
    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSTOR GATE 审中-公开

    公开(公告)号：US20200075609A1

    公开(公告)日：2020-03-05

    申请号：US16114272

    申请日：2018-08-28

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Seiyon Kim ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  G11C11/22

    Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

    Memory devices based on capacitors with built-in electric field
    10.
    发明授权
    Memory devices based on capacitors with built-in electric field 有权

    公开(公告)号：US11171145B2

    公开(公告)日：2021-11-09

    申请号：US16016375

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Sou-Chi Chang ,  Uygar Avci ,  Daniel H. Morris ,  Seiyon Kim ,  Ashish V. Penumatcha ,  Ian A. Young

    IPC: H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

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