公开(公告)号：US11699756B2

公开(公告)日：2023-07-11

申请号：US17541199

申请日：2021-12-02

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7846 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42364

摘要： Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US11482457B2

公开(公告)日：2022-10-25

申请号：US16640470

申请日：2017-09-22

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Cory C. Bomberger ,  Anand S. Murthy

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

摘要： Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.

公开(公告)号：US11101350B2

公开(公告)日：2021-08-24

申请号：US15930627

申请日：2020-05-13

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Tahir Ghani ,  Harold W. Kennel

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US11004954B2

公开(公告)日：2021-05-11

申请号：US16326844

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Karthik Jambunathan ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Tahir Ghani

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00

摘要： Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

公开(公告)号：US20210074823A1

公开(公告)日：2021-03-11

申请号：US17082726

申请日：2020-10-28

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Karthik Jambunathan ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Patrick Morrow ,  Mauro J. Kobrinsky

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

摘要： Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

公开(公告)号：US20200220014A1

公开(公告)日：2020-07-09

申请号：US16640465

申请日：2017-09-27

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

摘要： Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US10573750B2

公开(公告)日：2020-02-25

申请号：US15779485

申请日：2015-12-24

申请人： Intel Corporation

发明人： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165

摘要： Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US09997414B2

公开(公告)日：2018-06-12

申请号：US15125437

申请日：2014-06-24

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423

CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

公开(公告)号：US11264501B2

公开(公告)日：2022-03-01

申请号：US16637213

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Rishabh Mehandru ,  Anand Murthy ,  Karthik Jambunathan ,  Cory Bomberger

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L21/8238

摘要： Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.

公开(公告)号：US11251302B2

公开(公告)日：2022-02-15

申请号：US16640465

申请日：2017-09-27

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

摘要： Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.