- 专利标题: Ge/SiGe-channel and III-V-channel transistors on the same die
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申请号: US15125437申请日: 2014-06-24
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公开(公告)号: US09997414B2公开(公告)日: 2018-06-12
- 发明人: Glenn A. Glass , Anand S. Murthy , Karthik Jambunathan
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Finch & Maloney PLLC
- 国际申请: PCT/US2014/043821 WO 20140624
- 国际公布: WO2015/199655 WO 20151230
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L27/00 ; H01L29/00 ; H01L21/8238 ; H01L21/84 ; H01L29/66 ; H01L27/092 ; H01L29/786 ; H01L27/12 ; H01L29/10 ; H01L21/02 ; H01L29/06 ; H01L29/165 ; H01L29/205 ; H01L29/423
摘要:
Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
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