公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

摘要： Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US20230420507A1

公开(公告)日：2023-12-28

申请号：US17847559

申请日：2022-06-23

申请人： Intel Corporation

发明人： Ashish Agrawal ,  Anand Murthy ,  Jack T. Kavalieros ,  Rajat K. Paul ,  Susmita Ghose ,  Seung Hoon Sung

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

摘要： Semiconductor devices on a substrate with an alternative crystallographic surface orientation. Example devices includes gate-all-around (e.g., nanoribbon and nanosheet) and forksheet transistors. In an example, a substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating silicon germanium (SiGe) or germanium tin (GeSn) and silicon (Si) semiconductor layers. P-channel transistors may be formed using SiGe or GeSn nanoribbons while n-channel transistors are formed from Si nanoribbons. The crystallographic surface orientation of the SiGe or GeSn nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the SiGe or GeSn nanoribbons and improved device performance.

公开(公告)号：US11769789B2

公开(公告)日：2023-09-26

申请号：US16368450

申请日：2019-03-28

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC分类号： H01G4/30 ,  H10B51/00 ,  H01L23/522 ,  H01L49/02 ,  H01G4/012

CPC分类号： H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

摘要： A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

公开(公告)号：US11735670B2

公开(公告)日：2023-08-22

申请号：US17497864

申请日：2021-10-08

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20230057464A1

公开(公告)日：2023-02-23

申请号：US17981561

申请日：2022-11-07

申请人： Intel Corporation

发明人： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L27/108 ,  H01L21/822 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06

摘要： Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

公开(公告)号：US11515402B2

公开(公告)日：2022-11-29

申请号：US16081403

申请日：2016-03-30

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Robert B. Turkot ,  Marko Radosavljevic ,  Han Wui Then ,  Willy Rachmady ,  Sansaptak Dasgupta ,  Jack T. Kavalieros

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/49

摘要： The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.

公开(公告)号：US11322620B2

公开(公告)日：2022-05-03

申请号：US16648974

申请日：2017-12-29

申请人： Intel Corporation

发明人： Van H. Le ,  Ashish Agrawal ,  Seung Hoon Sung ,  Abhishek A. Sharma ,  Ravi Pillarisetty

IPC分类号： H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

摘要： Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US11233148B2

公开(公告)日：2022-01-25

申请号：US16649304

申请日：2017-11-06

申请人： INTEL CORPORATION

发明人： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

摘要： Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC分类号： H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

摘要： An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US11152290B2

公开(公告)日：2021-10-19

申请号：US16094817

申请日：2016-06-29

申请人： Intel Corporation

发明人： Benjamin Chu-Kung ,  Van H. Le ,  Willy Rachmady ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ashish Agrawal ,  Seung Hoon Sung

IPC分类号： H01L23/498 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

摘要： A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.