公开(公告)号：US11409935B2

公开(公告)日：2022-08-09

申请号：US16649800

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Srinivasa Chaitanya Gadigatla ,  Tamanna Husain ,  Abhinand Ramakrishnan ,  James Graeber ,  Kohinoor Basu

IPC: G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  H01L27/02 ,  G06F111/20 ,  G06F119/12

Abstract: An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.