公开(公告)号：US20240339432A1

公开(公告)日：2024-10-10

申请号：US18749542

申请日：2024-06-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1146 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14132 ,  H01L2224/16148 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/3511

摘要： A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.

公开(公告)号：US12087727B2

公开(公告)日：2024-09-10

申请号：US17872023

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1146 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14132 ,  H01L2224/16148 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/3511

摘要： A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

公开(公告)号：US12033969B2

公开(公告)日：2024-07-09

申请号：US17873673

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/06179 ,  H01L2224/09181 ,  H01L2224/09515 ,  H01L2224/10126 ,  H01L2224/13012 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/1715 ,  H01L2224/17181 ,  H01L2224/17515 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2924/3512

摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

公开(公告)号：US11705407B2

公开(公告)日：2023-07-18

申请号：US17685378

申请日：2022-03-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50

摘要： A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

公开(公告)号：US20220375806A1

公开(公告)日：2022-11-24

申请号：US17874326

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chien-Yuan Huang

IPC分类号： H01L23/04 ,  H01L23/538 ,  H01L21/52 ,  H01L25/065 ,  H01L23/31

摘要： A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.

公开(公告)号：US10770405B2

公开(公告)日：2020-09-08

申请号：US15609206

申请日：2017-05-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Hui Huang ,  Da-Cyuan Yu ,  Kuan-Yu Huang ,  Pai Yuan Li ,  Hsiang-Fan Lee

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

公开(公告)号：US20200006181A1

公开(公告)日：2020-01-02

申请号：US16177637

申请日：2018-11-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

摘要： A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US12002721B2

公开(公告)日：2024-06-04

申请号：US17874326

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chien-Yuan Huang

IPC分类号： H01L25/065 ,  H01L21/52 ,  H01L23/04 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L23/04 ,  H01L21/52 ,  H01L23/3121 ,  H01L23/538 ,  H01L25/0655

摘要： A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.

公开(公告)号：US20230307382A1

公开(公告)日：2023-09-28

申请号：US18327076

申请日：2023-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50

摘要： A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

公开(公告)号：US11764123B2

公开(公告)日：2023-09-19

申请号：US17857166

申请日：2022-07-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Hui Huang ,  Shang-Yun Hou ,  Tien-Yu Huang ,  Heh-Chang Huang ,  Kuan-Yu Huang ,  Shu-Chia Hsu ,  Yu-Shun Lin

IPC分类号： H01L23/31 ,  H01L25/16

CPC分类号： H01L23/3185 ,  H01L25/167

摘要： A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.